RT9073A
11
DS9073A-03 June 2017 www.richtek.com
©
Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Application Information
Like any low dropout linear regulator, the RT9073A’s
external input and output capacitors must be properly
selected for stability and performance. Use a 1μF or larger
input capacitor and place it close to the IC's VIN and GND
pins. Any output capacitor meeting the minimum 1mΩ
ESR (Equivalent Series Resistance) and effective
capacitance larger than 1μF requirement may be used.
Place the output capacitor close to the IC's VOUT and
GND pins. Increasing capacitance and decreasing ESR
can improve the circuit's PSRR and line transient response.
Enable
The RT9073A has an EN pin to turn on or turn off the
regulator, When the EN pin is in logic high, the regulator
will be turned on. The shutdown current is almost 0μA
typical. The EN pin may be directly tied to V
IN
to keep the
part on. The Enable input is CMOS logic and cannot be
left floating.
Current Limit
The RT9073A contains an independent current limiter,
which monitors and controls the pass transistor's gate
voltage, limiting the output current to 0.35A (typ.). The
current limiting level is reduced to around 250mA named
fold-back current limit when the output voltage is further
decreased. The output can be shorted to ground indefinitely
without damaging the part.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications the
maximum junction temperature is 125°C and T
A
is the
ambient temperature. The junction to ambient thermal
resistance, θ
JA
, is layout dependent. For ZQFN-4L 1x1
(ZDFN-4L 1x1) package, the thermal resistance, θ
JA
, is
226°C/W on a two-layer Richtek evaluation board. For
SC-82 (SSOT-24) package, the thermal resistance, θ
JA
,
is 345.6°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at T
A
= 25°C
can be calculated by the following formula :
P
D(MAX)
= (125°C − 25°C) / (226°C/W) = 0.44W for
ZQFN-4L 1x1 (ZDFN-4L 1x1) package
P
D(MAX)
= (125°C − 25°C) / (345.6°C/W) = 0.28W for
SC-82 (SSOT-24) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 1. Derating Curve of Maximum Power Dissipation
0.0
0.2
0.4
0.6
0.8
1.0
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
ZQFN-4L 1x1 (ZDFN-4L 1x1)
SC-82 (SSOT-24)
Four-Layer PCB for SC-82 package
Two-Layer Richtek EVB for ZQFN (ZDFN)- 4L 1x1
package
