10
FN6775.0
December 8, 2008
Functional Pin Descriptions
BOOT
High-Side Power MOSFET Driver Power-Supply Connection.
Connect a 0.1µF capacitor from BOOT to PHASE.
UGATE
High-Side Power MOSFET Driver Output. Connect to the
high-side N-Channel MOSFET gate.
LGATE
Low-Side Power MOSFET Driver Output. Connect to
low-side N-Channel MOSFET. LGATE drives between
VDDP and PGND.
PHASE
High-Side Power MOSFET Driver Source Connection.
Connect to the source of the high-side N-Channel MOSFET.
PGND
Power Ground. Connect PGND to the source of the low side
MOSFET.
CSOP
Charge Current-Sense Positive Input.
CSON
Charge Current-Sense Negative Input and system voltage
feedback.
CSIP
Input Current-Sense Positive Input.
CSIN
Input Current-Sense Negative Input.
DCIN
Charger Bias Supply Input. Bypass DCIN with a 0.1µF
capacitor to AGND.
ADET
AC Adapter Detection Input. Connect to a resistor divider
from the AC-adapter output.
ADPR
Adapter Present Output. This open drain output is high
impedance when ADET is greater than 3.2V. The ADPR
output remains low when the ISL9518 is powered down.
Connect a 10k pull-up resistor from ADPR to VSMB.
ACMON
Input Current Monitor Output. ACMON voltage equals
20 x (V
CSIP
- V
CSIN
).
VDD
Linear Regulator Output. VDD is the output of the 5.1V linear
regulator supplied from DCIN. VDD supplies regulated
power input for internal analog circuits. Connect a 4.7Ω
resistor from VDD to VDDP and a 1µF ceramic capacitor
from VDD to AGND.
VDDP
VDDP directly supplies the LGATE driver and the BOOT
strap diode. Bypass with a 1µF ceramic capacitor from
VDDP to PGND.
ICOMP
Output of the Current Control error amplifier. See “Loop
Compensation Design” on page 20 for details on selecting
compensation components.
VCOMP
Output of the Voltage loop error amplifier. See “Loop
Compensation Design” on page 20 for details on selecting
compensation components.
VFB
Negative input to the Min System Voltage and Max System
Voltage control error amplifier.
VREF
Output of an internal precision voltage reference.
TRKLN
Open drain out that goes low when the charger is in
trickle-charge mode.
BGATE
Gate drive for the battery connection PFET. This pin can go
high to disconnect the battery, low to connect the battery or
operate in a linear mode to regulate minimum system
voltage during trickle charge. It is also the compensation
point for the Min System Voltage regulation loop.
SGATE
SGATE is the AC adapter power source select output. The
SGATE pin drives back to back external P-MOSFETs used to
connect and disconnect the AC adapter to the NVDC charger
input. SGATE is controlled by the SMBus and the ADET state.
VSMB
SMBus interface Supply Voltage Input. Bypass with a 0.1µF
capacitor to AGND.
SDA
SMBus Data I/O. Open-drain Output. Connect an external
pull-up resistor according to SMBus specifications.
SCL
SMBus Clock Input. Connect an external pull-up resistor
according to SMBus specifications.
AGND
Analog Ground. Connect to PGND close to the output
capacitor.
Backside Paddle
Connects the backside paddle to AGND.
ISL9518, ISL9518A
11
FN6775.0
December 8, 2008
Theory of Operation
Introduction
The ISL9518 differs from the ISL9518A only in the default
states of the internal registers at power-up. ISL9518 defaults
are for systems with an 8.4V (2-cell) battery and ISL9518A
defaults are for systems with a 12.6V battery (3-cell). Unless
otherwise noted, all specifications and descriptions of
ISL9518 refer to both the ISL9518 and ISL9518A.
A high efficiency synchronous buck converter is used to
control the system voltage up to 19.2V and charging current
up to 8A. The ISL9518 also has input current limiting up to
8.064A (or higher with lower values of sense resistor). The
Input current limit, charge current limit, minimum and
maximum system voltage are set by internal registers written
with SMBus. The ISL9518 “Typical Application Circuit” is
shown in Figure 2.
The ISL9518 charges the battery with constant charge
current, set by the ChargeCurrent register, until the battery
voltage rises to a voltage set by the MaxSystemVoltage
register. The charger will then operate at a constant voltage.
The adapter current is monitored and if the adapter current
rises to the limit set by the InputCurrent register, system
voltage and battery charge current are reduced to limit
adapter current. If battery voltage is below the min system
voltage, the trickle charge system is activated.
The ISL9518 features two voltage regulation loops and two
current regulation loops. The max system voltage loop
controls the voltage at CSON with a precision voltage divider
to the voltage error amplifier GM2. The min system voltage
prevents the system voltage from dropping below a minimum
value even if a deeply discharged battery is inserted that is
below the minimum. The Charge Current regulation loop
limits the battery charging current delivered to the battery to
ensure that it never exceeds the current set by the
ChargeCurrent register. The Input Current regulation loop
limits the current drawn from the AC-adapter to ensure that it
never exceeds the limit set by the InputCurrent register to
prevent adapter overload.
PWM Control
The ISL9518 employs a fixed frequency pulse width
modulator (PWM) with feed forward. The switching
frequency can be reduced with an SMBus command for
improved light load efficiency
AC-adapter Detection
AC-adapter voltage is connected through a resistor divider to
ADET to detect when AC power is available, as shown in
Figure 2. ADPR is an open-drain output and is active low
when ADET is less than V
th,fall
, and high Z when ADET is
above V
th,rise
. The ADET rising threshold is 3.2V (typ) with
57mV hysteresis. ADET must be above the threshold to
Enable the output voltage.
Current Measurement
ACMON is an output voltage that is proportional to the
adapter current being sensed across CSIP and CSIN. The
output voltage range is 0.1V to 3.2V. The voltage of ACMON
is given by Equation 1:
where I
INPUT
is the DC current drawn from the AC-adapter.
A capacitor is required at the ACMON output to stabilize the
ACMON amplifier and to minimize switching noise.
VDD Regulator
VDD provides a 5.1V supply voltage from the internal LDO
regulator from DCIN and can deliver up to 30mA of
continuous current. VDD also supplies power to VDDP
through a low pass filter as shown in the “Typical Application
Circuit” in Figure 2. The MOSFET drivers are powered by
VDDP. Bypass VDDP and VDD with a 1µF capacitor.
VSMB Supply
The VSMB input provides power to the SMBus interface.
Connect an external supply to VSMB to keep the SMBus
interface active while the supply to DCIN is removed. When
VSMB is biased, the internal registers are maintained. Bypass
VSMB to AGND with a 0.1µF or greater ceramic capacitor.
SGATE Function
If ADET > 3.2V and VDD > 4.5V and ISOLATE_ADAPTER bit
is 0 (default state) then SGATE will be ON (meaning SGATE
will be driven to ground turning on the inrush limit and the
adapter isolation FETs ON). In all other cases, SGATE is OFF
(meaning the chip will not pull-down SGATE and the off chip
resistor will pull the gates of the in-rush limit and adapter
isolation FETs to their sources, turning them OFF).
BGATE Function
The BGATE pin drives the gate of an external PFET to
control the minimum system voltage. If a battery is
connected that is discharged below the value set in the
MinSystemVoltage register, BGATE controls the system
voltage at the value set in the MinSystemVoltage register.
Trickle Charging
If a battery that is discharged below the value set in the
MinSystemVoltage register is connected to the system, the
trickle charge system is activated. In trickle charge mode,
the charge current is reduced to 256mA. The value in the
ChargeCurrent register is not changed. The BGATE FET is
controlled in a linear mode to regulate the system voltage at
min system voltage and to drop voltage between the min
system voltage and the battery. This state is communicated
to the host system by the trickle bit in the control register and
a low state on the TRKLN pin.
When the battery is charged to the min system voltage, the
BGATE FET becomes fully enhanced and BGATE is pulled
more than 5V below the system voltage. This changes the
ACMON 20 I
INPUT
R
S1
⋅⋅=
(EQ. 1)
ISL9518, ISL9518A
12
FN6775.0
December 8, 2008
charge mode from trickle to fast charge. The charge current
is increased to the value in the ChargeCurrent register. The
TRKLN output goes hi and the trickle bit in the control
register goes low.
Short Circuit Protection and 0V Battery Charging
If a battery is connected that is completely discharged or a
short circuit, the trickle charge system is activated. The
Charge Current is reduced to 256mA and BGATE controls
the BGATE FET to maintain system voltage at the value in
the MinSystemVoltage register.
Over-Temperature Protection
If the die temp exceeds +150°C, it turns both of the
synchronous buck FETs off. The system bus and the battery
charging are disabled. Once the die temp drops below
+125°C, system bus regulation and battery charging will
start-up again.
The System Management Bus
The System Management Bus (SMBus) is a 2-wire bus that
supports bidirectional communications. The protocol is
described briefly here. More detail is available from
http://www.smbus.org/.
General SMBus Architecture
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 15.
.
START and STOP Conditions
As shown in Figure 16, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
Acknowledge
Each address and data transmission uses 9 clock pulses. The
ninth pulse is the acknowledge bit (ACK). After the start
condition, the master sends 7 slave address bits and a R/W
bit
during the next 8 clock pulses. During the ninth clock pulse, the
device that recognizes its own address holds the data line low
to acknowledge (as shown in Figure 17). The acknowledge bit
is also used by both the master and the slave to acknowledge
receipt of register addresses and data.
SMBus Transactions
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7 bits of slave address (0001001 for the ISL9518)
followed by the R/W
bit. The R/W bit is 0 for a write or 1 for a
read. If any slave devices on the SMBus bus recognize their
address, they will acknowledge by pulling the serial data (SDA)
line low for the last clock cycle in the control byte. If no slaves
exist at that address or are not ready to communicate, the data
line will be 1, indicating a Not Acknowledge condition.
VDD SMB
SDA
SCL
SCL
SMBUS MASTER
CPU
SDA
TO OTHER
SLAVE DEVICES
STATE
MACHINE
REGISTERS
MEMORY
ETC
OUTPUT
INPUT
SCL
CONTROL
SDA
CONTROL
OUTPUT
INPUT
SMBUS SLAVE
,
,
SCL
SDA
SMBUS SLAVE
STATE
MACHINE
REGISTERS
MEMORY
ETC
INPUT
OUTPUT
INPUT
OUTPUT
CONTROL
CONTROL
CONTROL
CONTROL
INPUT
OUTPUT
INPUT
OUTPUT
SDA
SCL
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
FIGURE 15. DATA VALIDITY
SDA
SCL
START
CONDITION
FIGURE 16. START AND STOP WAVEFORMS
STOP
CONDITION
SP
SDA
SCL
FIGURE 17. ACKNOWLEDGE ON THE I
2
C BUS
1
2
8
9
ACKNOWLEDGE
MSB
START
FROM SLAVE
ISL9518, ISL9518A

ISL9518AHRTZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Battery Management TQFN ISL9518A NOTEBOOK BATRY CHRGR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet