23
FN6775.0
December 8, 2008
C
ICOMP
should be chosen using Equation 26 to set
F
Z1
=F
DP
/10. The crossover frequency will be
approximately 2.5*F
DP
. The phase margin will be between
+10° and +40° depending on F
ZESR
.
Adapter Current Limit Control Loop
If the combined battery charge current and system load
current results in adapter current that equals the
programmed adapter current limit, ISL9518 will reduce the
current to the battery and/or reduce the output voltage to
hold the adapter current at the limit. Above the adapter
current limit, the minimum current buffer equals the output of
gm3 and ICOMP controls the charger output.
A filter should be added between R
S1
and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the cross over frequency and the switching
frequency (~100kHz).
The loop response equations, bode plots and the selection
of C
ICOMP
are the same as the charge current control loop
with loop gain reduced by the duty cycle. In other words, if
the duty cycle D = 50%, the loop gain will be 6dB lower than
the loop gain in Figure 24. This gives lower crossover
frequency and higher phase margin in this mode.
The current control loops can have the same gain if the Input
current sense resistor is larger than the charge current
sense resistor by the same ratio that input voltage is larger
than output voltage.
Min System Voltage Control Loop
The min system voltage control loop is only active when a
battery is connected that is discharged to a voltage below
the voltage in the MinSystemVoltage register. When it is
active, the ISL9518 reduces the charge current to 256mA
and controls the BGATE FET in the linear range to hold the
min system voltage on the system output. The reduced
charge current and active BGATE control are referred to in
this document as “Trickle Charge Mode”.
When the battery voltage is higher than min system voltage,
BGATE goes approximately 7V below the system voltage (at
CSON) to fully enhance the BGATE FET.
When the battery voltage is less than the min system voltage,
the min system voltage loop controls the voltage on BGATE to
hold the system voltage at the programmed min system
voltage. The difference between the min system voltage and
the battery voltage drops across the BGATE FET.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dV/dt and di/dt, such as
gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
AGND and VDD Pins
At least one high quality ceramic decoupling capacitor
should be used to cross these two pins. The decoupling
capacitor can be put close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
-60
-40
-20
0
20
40
60
0.01 0.1 1 10 100 1k
FREQUENCY (kHz)
GAIN (dB)
LOOP
MODULATOR
COMPENSATOR
F
DP
F
ZESR
F
Z1
F
FILTER
FIGURE 24. CHARGE CURRENT LOOP BODE PLOTS
C
ICOMP
4gm1⋅
2π F
DP
10⁄⋅
---------------------------------
=
(EQ. 26)
FIGURE 25. ADAPTER CURRENT LIMIT LOOP
L
C
ICOMP
R
BAT
ICOMP
PHASE
R
ESR
C
O
11
S
+
-
0.25
+
-
gm3
DCIN
CSIN
+
-
20
CSIP
C
F1
R
F1
R
S2
CSON
+
-
20
CSOP
C
F2
R
F2
ACDAC
Σ
ISL9518, ISL9518A
