19
FN6775.0
December 8, 2008
600kHz operation with low core loss. The core must be large
enough not to saturate at the peak inductor current I
Peak
in
Equation 4:
Inductor saturation can lead to cascade failures due to very
high currents. Conservative design limits the peak current in
the inductor to less than 90% of the rated saturation current.
Crossover frequency is heavily dependent on the inductor
value. F
CO
should be less than 20% of the switching
frequency and a conservative design has F
CO
less than
10% of the switching frequency. The highest F
CO
is in
voltage control mode with the battery removed and may be
calculated (approximately) from Equation 5:
Output Capacitor Selection
In Narrow VDC systems, one or more capacitors are
connected at the charger output (CSON) and a large number
of capacitors are connected to the system voltage output.
Most of the system voltage capacitors are placed near the
inputs to the system and core regulators. Some capacitance
(on the order of 20µF to 100µF) with low ESR should be
placed near the inductor and FETs to provide a path for
switching currents that is short and has a small area.
A combination of 0.1µF, 10µF ceramic capacitors and
organic polymer capacitors is a good choice for capacitors
near the ISL9518 and the inputs to the other system
regulators. Organic polymer capacitors have high
capacitance with small size and have a significant equivalent
series resistance (ESR). Although ESR adds to ripple
voltage, it also creates a high frequency zero that helps the
closed loop operation of the buck regulator.
MOSFET Selection
The Notebook battery charger synchronous buck converter
has the input voltage from the AC-adapter output. The
maximum AC-adapter output voltage does not exceed 25V.
Therefore, 30V logic MOSFET should be used.
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous
buck converter is equal to the AC-adapter output voltage,
which is relatively constant. The maximum efficiency is
achieved by selecting a high side MOSFET that has the
conduction losses equal to the switching losses. Switching
losses in the low-side FET are very small. The choice of
low-side FET is a trade-off between conduction losses
(r
DS(ON)
) and cost. A good rule of thumb for the r
DS(ON)
of
the low-side FET is 2x the r
DS(ON)
of the high-side FET.
The LGATE gate driver can drive sufficient gate current to
switch most MOSFETs efficiently. However, some FETs may
exhibit cross conduction (or shoot-through) due to current
injected into the drain-to-source parasitic capacitor (C
gd
) by
the high dV/dt rising edge at the phase node when the high
side MOSFET turns on. Although LGATE sink current
(1.8A typical) is more than enough to switch the FET off
quickly, voltage drops across parasitic impedances between
LGATE and the MOSFET can allow the gate to rise during
the fast rising edge of voltage on the drain. MOSFETs with
low threshold voltage (<1.5V) and low ratio of C
gs
/C
gd
(<5)
and high gate resistance (>4Ω) may be turned on for a few
ns by the high dV/dt (rising edge) on their drain. This can be
avoided with higher threshold voltage and C
gs
/C
gd
ratio.
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage, as shown in
Equation 6:
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include the MOSFET internal gate resistance, gate charge,
threshold voltage, stray inductance and the pull-up and
pull-down resistance of the gate driver.
The following switching loss calculation (Equation 7)
provides a rough estimate.
where the following are the peak gate-drive source/sink
current of Q
1
, respectively:
•Q
gd
: drain-to-gate charge,
•Q
rr
: total reverse recovery charge of the body-diode in
low-side MOSFET,
•I
LV
: inductor valley current,
•I
LP
: Inductor peak current,
•I
g,sink
•I
g
,
source
Low switching loss requires low drain-to-gate charge Q
gd
.
Generally, the lower the drain-to-gate charge, the higher the
ON-resistance. Therefore, there is a trade-off between the
ON-resistance and drain-to-gate charge. Good MOSFET
selection is based on the Figure of Merit (FOM), which is a
product of the total gate charge and ON-resistance. Usually,
the smaller the value of FOM, the higher the efficiency for
the same application.
I
PEAK
I
OUT MAX,
1
2
---
+ I
RIPPLE
⋅=
(EQ. 4)
F
CO
511R
SENSE
⋅⋅
2π L⋅
------------------------------------------ -
=
(EQ. 5)
P
Q1 conduction,
V
OUT
V
IN
----------------
I
SYS
I+
BAT
()
2
r
DS ON()
⋅⋅=
(EQ. 6)
P
Q1 Switching,
1
2
---
V
IN
I
LV
f
sw
Q
gd
I
g source,
-------------------------
⎝⎠
⎜⎟
⎛⎞
1
2
---
V
IN
I
LP
f
sw
Q
gd
I
gksin,
-----------------
⎝⎠
⎜⎟
⎛⎞
Q
rr
V
IN
f
sw
++
=
(EQ. 7)
ISL9518, ISL9518A
