ZL40209 Data Sheet
6
Microsemi Corporation
3.0 Functional Description
The ZL40209 is an LVPECL clock fan out buffer with two input and six output clock drivers capable of operating at
frequencies up to 750MHz.
The ZL40209 provides an internal input termination netwo
rk for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40209 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40209 is designed to fan out
low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
Receiver
clk_n
50
clk_p
Vt
50
Bias
ctrl
Figure 3 - Simplified Diagram of Input Stage
3.2 Clock Input Selection
The select line chooses which input clock is routed to the outputs.
Table 1 - Input Selection
Sel Active Input
0 clk0
1 clk1
The following figure shows the expected clock
switching performance. The output stops at the first falling edge of
the initial clock after the select pin changes state. During switching there will be a short time when the output clock
is not toggling. After this delay, the output will start toggling again with a rising edge of the newly selected clock.
ZL40209 Data Sheet
7
Microsemi Corporation
This behavior is independent of the frequencies of the input clocks. For instance, the two clocks could be at
different frequencies and the behavior would still be consistent with this figure.
2 µs
clk0
clk1
sel
outn
1
0
Figure 4 - Output During Clock Switch - Both Clocks Running
3.2.1 Clock Input Terminations
The following figures show how to connect various input clocks types to the fanout buffer. Each diagram shows how
to configure the Vt and ctrl pins along along with the other necessary components and their values.
For input clock types where the ctrl
pin is "1" and the Vt pin is not connected, the Vt pin can be instead connected
to V
DD
with a capacitor.
In addition, a capacitor can also help in Figure 5 between Vt a
nd V
DD
. This capacitor will minimize the noise at the
point between the two internal termination resistors an
d improve the overall performance of the device.
LVPECL
Driver
R
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
For 3.3 V: R= 50 Ohms
For 2.5 V: R= 22 Ohms
22 Ohms
22 Ohms
Not recommended for VDD_driver=2.5V
Figure 5 - Clock Input - LVPECL - DC Coupled
LVPECL
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
For 3.3 V: R= 150 Ohms
For 2.5 V: R= 85 Ohms
NC
RR
22 Ohms
22 Ohms
LVDS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
NC
ZL40209 Data Sheet
8
Microsemi Corporation
Figure 6 - Clock Input - LVPECL - AC Coupled
Figure 7 - Clock Input - LVDS - DC Coupled

ZL40209LDG1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 2:6 LVPECL Fanout Buffer w/Int. Term.
Lifecycle:
New from this manufacturer.
Delivery:
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