Unless the load is being performed to Device or Strongly-Ordered memory, there should be no
implications from the repetition of the load. In the unlikely event that the load is being
performed to Device or Strongly-Ordered memory, the repeated read can result in the final
stack-pointer value being different than had only a single load been performed.
Interruption of the two write-back forms of the instruction can result in both the base register
value and final stack-pointer value being incorrect. This can result in apparent stack corruption
and subsequent unintended modification of memory.
Workaround: Both issues may be worked around by replacing the direct load to the stack-pointer, with an
intermediate load to a general-purpose register followed by a move to the stack-pointer.
If repeated reads are acceptable, then the base-update issue may be worked around by
performing the stack pointer load without the base increment followed by a subsequent ADD or
SUB instruction to perform the appropriate update to the base register.
e4588: DMAMUX: When using PIT with "always enabled" request, DMA request does
not deassert correctly
Errata type: Errata
Description: The PIT module is not assigned as a stand-alone DMA request source in the DMA request
mux. Instead, the PIT is used as the trigger for the DMAMUX periodic trigger mode. If you want
to use one of the PIT channels for periodic DMA requests, you would use the periodic trigger
mode in conjunction with one of the "always enabled" DMA requests. However, the DMA
request does not assert correctly in this case.
Instead of sending a single DMA request every time the PIT expires, the first time the PIT
triggers a DMA transfer the "always enabled" source will not negate its request. This results in
the DMA request remaining asserted continuously after the first trigger.
Workaround: Use of the PIT to trigger DMA channels where the major loop count is greater than one is not
recommended. For periodic triggering of DMA requests with major loop counts greater than
one, we recommended using another timer module instead of the PIT.
If using the PIT to trigger a DMA channel where the major loop count is set to one, then in
order to get the desired periodic triggering, the DMA must do the following in the interrupt
service routine for the DMA_DONE interrupt:
1. Set the DMA_TCDn_CSR[DREQ] bit and configure DMAMUX_CHCFGn[ENBL] = 0
2. Then again DMAMUX_CHCFGn[ENBL] = 1, DMASREQ=channel in your DMA DONE
interrupt service routine so that "always enabled" source could negate its request then DMA
request could be negated.
This will allow the desired periodic triggering to function as expected.
e6358: ENET: Write to Transmit Descriptor Active Register (ENET_TDAR) is ignored
Errata type: Errata
Description: If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously detected as not set
during a prior frame transmission, then the ENET_TDAR[TDAR] bit is cleared at a later time,
even if additional TxBDs were added to the ring and the ENET_TDAR[TDAR] bit is set. This
results in frames not being transmitted until there is a 0-to-1 transition on ENET_TDAR[TDAR].
Mask Set Errata for Mask 5N22D, Rev 19 DEC 2013
4 Freescale Semiconductor, Inc.
