MK50DN512CLL10 Datasheet MK50DX256CLK10, MK50DN512CMC10, MK50DX256CMC10 | P7-P9

e6573: JTAG: JTAG TDO function on the PTA2 disables the pull resistor

Errata type: Errata

Description: The JTAG TDO function on the PTA2 pin disables the pull resistor, but keeps the input buffer

enabled. Because the JTAG will tri-state this pin during JTAG reset (or other conditions), this

pin will float with the input buffer enabled. If the pin is unconnected in the circuit, there can be

increased power consumption in low power modes for some devices.

Workaround: Disable JTAG TDO functionality when the JTAG interface is not needed and left floating in a

circuit. Modify the PORTA_PCR2 mux before entering low power modes. Set the mux to a pin

function other than ALT7. If set up as a digital input and left unconnected in the circuit, then a

pull-up or pull-down should be enabled. Alternatively, an external pull device or external source

can be added to the pin.

Note: Enabling the pull resistor on the JTAG TDO function violates the JTAG specification.

e4590: MCG: Transitioning from VLPS to VLPR low power modes while in BLPI clock

mode is not supported.

Errata type: Errata

Description: Transitioning from VLPS mode back to VLPR (LPWUI control bit = 0) while using BLPI clock

mode only, is not supported. During Fast IRC startup, the output clock frequency may exceed

the maximum VLPR operating frequency. This does not apply to the BLPE clock mode.

Workaround: There are two options for workarounds

a) Exit to Run instead of VLPR. Before entering VLPR set the LPWUI bit so that when exiting

VLPS mode the MCU exits to RUN mode instead of VLPR mode. With LPWUI set any interrupt

will exit VLPR or VLPS back into RUN mode. To minimize the impact of the higher RUN

current re-enter VLPR quickly.

b) Utilize MCG clock mode BLPE when transitioning from VLPS to VLPR modes.

e5130: SAI: Under certain conditions, the CPU cannot reenter STOP mode via an

asynchronous interrupt wakeup event

Errata type: Errata

Description: If the SAI generates an asynchronous interrupt to wake the core and it attempts to reenter

STOP mode, then under certain conditions the STOP mode entry is blocked and the

asynchronous interrupt will remain set.

This issue applies to interrupt wakeups due to the FIFO request flags or FIFO warning flags

and then only if the time between the STOP mode exit and subsequent STOP mode reentry is

less than 3 asynchronous bit clock cycles.

Workaround: Ensure that at least 3 bit clock cycles elapse following an asynchronous interrupt wakeup

event, before STOP mode is reentered.

Mask Set Errata for Mask 5N22D, Rev 19 DEC 2013

Freescale Semiconductor, Inc. 7

e3981: SDHC: ADMA fails when data length in the last descriptor is less or equal to 4

bytes

Errata type: Errata

Description: A possible data corruption or incorrect bus transactions on the internal AHB bus, causing

possible system corruption or a stall, can occur under the combination of the following

conditions:

1. ADMA2 or ADMA1 type descriptor

2. TRANS descriptor with END flag

3. Data length is less than or equal to 4 bytes (the length field of the corresponding descriptor

is set to 1, 2, 3, or 4) and the ADMA transfers one 32-bit word on the bus

4. Block Count Enable mode

Workaround: The software should avoid setting ADMA type last descriptor (TRANS descriptor with END

flag) to data length less than or equal to 4 bytes. In ADMA1 mode, if needed, a last NOP

descriptor can be appended to the descriptors list. In ADMA2 mode this workaround is not

feasible due to ERR003983.

e3982: SDHC: ADMA transfer error when the block size is not a multiple of four

Errata type: Errata

Description: Issue in eSDHC ADMA mode operation. The eSDHC read transfer is not completed when

block size is not a multiple of 4 in transfer mode ADMA1 or ADMA2. The eSDHC DMA

controller is stuck waiting for the IRQSTAT[TC] bit in the interrupt status register.

The following examples trigger this issue:

1. Working with an SD card while setting ADMA1 mode in the eSDHC

2. Performing partial block read

3. Writing one block of length 0x200

4. Reading two blocks of length 0x22 each. Reading from the address where the write

operation is performed. Start address is 0x512 aligned. Watermark is set as one word during

read. This read is performed using only one ADMA1 descriptor in which the total size of the

transfer is programmed as 0x44 (2 blocks of 0x22).

Workaround: When the ADMA1 or ADMA2 mode is used and the block size is not a multiple of 4, the block

size should be rounded to the next multiple of 4 bytes via software. In case of write, the

software should add the corresponding number of bytes at each block end, before the write is

initialized. In case of read, the software should remove the dummy bytes after the read is

completed.

For example, if the original block length is 22 bytes, and there are several blocks to transfer,

the software should set the block size to 24. The following data is written/stored in the external

memory:

4 Bytes valid data

Mask Set Errata for Mask 5N22D, Rev 19 DEC 2013

8 Freescale Semiconductor, Inc.

4 Bytes valid data

2 Bytes valid data + 2 Byte dummy data

4 Bytes valid data

2 Bytes valid data + 2 Byte dummy data

In this example, 48 (24 x 2) bytes are transferred instead of 44 bytes. The software should

remove the dummy data.

e4624: SDHC: AutoCMD12 and R1b polling problem

Errata type: Errata

Description: Occurs when a pending command which issues busy is completed. For a command with R1b

response, the proper software sequence is to poll the DLA for R1b commands to determine

busy state completion. The DLA polling is not working properly for the ESDHC module and

thus the DLA bit in PRSSTAT register cannot be polled to wait for busy state ompletion. This is

relevant for all eSDHC ports (eSDHC1-4 ports).

Workaround: Poll bit 24 in PRSSTAT register (DLSL[0] bit) to check that wait busy state is over.

e3977: SDHC: Does not support Infinite Block Transfer Mode

Errata type: Errata

Description: The eSDHC does not support infinite data transfers, if the Block Count register is set to one,

even when block count enable is not set.

Workaround: The following software workaround can be used instead of the infinite block mode:

1. Set BCEN bit to one and enable block count

2. Set the BLKCNT to the maximum value in Block Attributes Register (BLKATTR) (0xFFFFfor

65535 blocks)

e4627: SDHC: Erroneous CMD CRC error and CMD Index error may occur on sending

new CMD during data transfer

Errata type: Errata

Description: When sending new, non data CMD during data transfer between the eSDHC and EMMC card,

the module may return an erroneous CMD CRC error and CMD Index error. This occurs when

the CMD response has arrived at the moment the FIFO clock is stopped. The following bits

after the start bit of the response are wrongly interpreted as index, generating the CRC and

Index errors.

The data transfer itself is not impacted.

The rate of occurrence of the issue is very small, as there is a need for the following

combination of conditions to occur at the same cycle:

Mask Set Errata for Mask 5N22D, Rev 19 DEC 2013

Freescale Semiconductor, Inc. 9

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

MK50DN512CLL10

Mfr. #:

Buy MK50DN512CLL10

Manufacturer:

NXP / Freescale

Description:

ARM Microcontrollers - MCU Kinetis 512K

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MK50DN512CLL10

MK50DN512CLL10

Products related to this Datasheet