LTC2302/LTC2306
10
23026fb
For more information www.linear.com/LTC2302
pin FuncTions
LTC2302
SDO (Pin 1): Three‑State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
V
DD
(Pin 3): 5V Supply. The range of V
DD
is 4.75V to 5.25V.
Bypass V
DD
to GND with a 0.1µF ceramic capacitor and a
10µF tantalum capacitor in parallel.
IN
+
, IN
–
(Pin 4, Pin 5): Positive (IN
+
) and Negative (IN
–
)
Differential Analog Inputs.
V
REF
(Pin 6): Reference Input. Connect an external refer‑
ence at V
REF
. The range of the external reference is 0.1V
to V
DD
. Bypass to GND with a minimum 10µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OV
DD
(Pin 10): Output Driver Supply. Bypass OV
DD
to
GND with a 0.1µF ceramic capacitor close to the pin. The
range of OV
DD
is 2.7V to 5.25V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
LTC2306
SDO (Pin 1): Three‑State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends
.
V
DD
(Pin 3): 5V Supply. The range of V
DD
is 4.75V to 5.25V.
Bypass V
DD
to GND with a 0.1µF ceramic capacitor and a
10µF tantalum capacitor in parallel.
CH0, CH1 (Pin 4, Pin 5): Channel 0 and Channel 1 Analog
Inputs. CH0, CH1 can be configured as single‑ended or
differential input channels. See the Analog Input Multi
‑
plexer section.
V
REF
(Pin 6): Reference Input. Connect an external refer‑
ence at V
REF
.The range of the external reference is 0.1V
to V
DD
. Bypass to GND with a minimum 10µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
configures the ADC and is latched on the rising edge of
the first 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OV
DD
(Pin 10): Output Driver Supply. Bypass OV
DD
to
OGND with a 0.1µF ceramic capacitor close to the pin.
The range of OV
DD
is 2.7V to 5.5V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
