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LTC2302CDD#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC2302/LTC2306
13
23026fb
For more information www.linear.com/LTC2302
applicaTions inForMaTion
Overview
The LTC2302/LTC2306 are low noise, 500ksps, 1‑/2‑chan
‑
nel, 12‑bit successive approximation register (SAR) A/D
converters. The LTC2306 includes a 2‑channel analog
input multiplexer (MUX) while the LTC2302 includes an
input MUX that allows the polarity of the differential input
to be selected. Both ADCs include an SPI‑compatible se
‑
rial port for easy data transfers and can operate in either
unipolar or bipolar mode. Unipolar mode should be used
for single‑ended operation with the LTC2306, since single‑
ended input signals are always referenced to GND. The
LTC2302/LTC2306 can be put into a power‑down sleep
mode during idle periods to save power.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6‑bit input word (D
IN
)
at the SDI input configures the MUX and programs vari
‑
ous modes of operation. As the D
IN
bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the D
IN
word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample‑and‑hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12‑bit capacitive
charge‑redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most significant bit (MSB) to the least significant
bit (LSB). The sampled input is successively compared with
binary weighted charges supplied by the capacitive DAC
using a differential comparator. At the end of a conver
‑
sion, the DAC output balances the analog input. The SAR
contents (a 12‑bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
Programming the LTC2306 and LTC2302
The software compatible LTC2302/LTC2306/LTC2308
family features a 6‑bit D
IN
word to program various modes
of operation. Don’t care bits (X) are ignored. The SDI data
bits are loaded on the rising edge of SCK, with the S/D bit
loaded on the first rising edge (see Figure 6 in the Timing
and Control section). The input data word for the LTC2306
is defined as follows:
S/D O/S X X UNI X
S/D = SINGLE‑ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
UNI = UNIPOLAR/BIPOLAR BIT
X = DON’ T CARE
For the LTC2302, the input data word is defined as:
X O/S X X UNI X
LTC2302/LTC2306
14
23026fb
For more information www.linear.com/LTC2302
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Figure 1a. Example MUX Configurations
Figure 1b. Changing the MUX Assignment “On the Fly”
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and O/S
bits of the D
IN
word for the LTC2306 and the O/S bit of the
D
IN
word for the LTC2302. Table 1 and Table 2 list MUX
configurations for all combinations of the configuration
bits. Figure 1a shows several possible MUX configurations
and Figure 1b shows how the MUX can be reconfigured
from one conversion to the next.
Driving the Analog Inputs
The analog inputs of the LTC2302/LTC2306 are easy to
drive. Each of the analog inputs of the LTC2306 (CH0
and CH1) can be used as a single‑ended input relative
to GND or as a differential pair. The analog inputs of the
LTC2302 (IN
+
, IN
–
) are always configured as a differential
pair. Regardless of the MUX configuration, the “+” and “–”
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the sample‑and‑hold cir
‑
cuit. The inputs draw only one small current spike while
charging the sample‑and‑hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
driving circuit is low, the ADC inputs can be driven directly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
CH0
CH1
(–) GND
2 Single-Ended
+
1 Differential
+ (
–
)
+
LTC2306 LTC2306
23026 F01a
–
(
+
)
{
CH0
CH1
1 Differential
+ (
–
)
LTC2302
–
(
+
)
{
IN
+
IN
–
CH0
CH1
(–) GND
LTC2306
2nd Conversion
+
1st Conversion
+
+
23026 F01b
–
{
CH0
CH1
LTC2306
S/D
0
0
1
1
O/S
0
1
0
1
CH0
+
–
+
CH1
–
+
+
WITH RESPECT
TO GND
NOTE: UNIPOLAR MODE SHOULD BE USED
FOR SINGLE-ENDED OPERATION, SINCE INPUT
SIGNALS ARE ALWAYS REFERENCED TO GND
Table 1. Channel Configuration
for the LTC2306
O/S
0
1
IN
+
+
–
IN
–
–
+
Table 2. Channel Configuration
for the LTC2302
LTC2302/LTC2306
15
23026fb
For more information www.linear.com/LTC2302
applicaTions inForMaTion
Figure 2b. Analog Input Equivalent Circuit for
Large Filter Capacitances
Figure 2a. Analog Input Equivalent Circuit
Reference
A low noise, stable reference is required to ensure full
performance. The LT
®
1790 and LT6660 are adequate
for most applications. The LT6660 is available in 2.5V,
3V, 3.3V and 5V versions, and the LT1790 is available in
1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V versions.
The exceptionally low input noise allows the input range to
be optimized for the application by changing the reference
voltage. The V
REF
input must be decoupled with a 10µF
capacitor in parallel with a 0.1µF capacitor, so verify that
the device providing the reference voltage is stable with
capacitive loads.
If the voltage reference is 5V and can supply 5mA, it can
be used for both V
REF
and V
DD
. V
DD
must be connected
to a clean analog supply, and a quiet 5V reference voltage
makes a convenient supply for this purpose.
Input Filtering
The noise and distortion of the input amplifier and other
circuitry must be considered since they will add to the ADC
noise and distortion. Therefore, noisy input circuitry should
be filtered prior to the analog inputs to minimize noise. A
simple 1‑pole RC filter is sufficient for many applications.
The analog inputs of the LTC2302/LTC2306 can be modeled
as a 55pF capacitor (C
IN
) in series with a 100Ω resistor
(R
ON
) as shown in Figure 2a. C
IN
gets switched to the
selected input once during each conversion. Large filter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
12‑bit resolution within the acquisition time (t
ACQ
) if DC
accuracy is important.
When using a filter with a large C
FILTER
value (e.g., 1µF),
the inputs do not completely settle and the capacitive in
‑
put switching currents are averaged into a net DC current
(I
DC
). In this case, the analog input can be modeled by an
equivalent resistance (R
EQ
= 1/(f
SMPL
• C
IN
)) in series with
an ideal voltage source (V
REF
/2) as shown in Figure 2b.
The magnitude of the DC current is then approximately
I
DC
= (V
IN
– V
REF
/2)/R
EQ
, which is roughly proportional
to V
IN
. To prevent large DC drops across the resistor
R
FILTER
, a filter with a small resistor and large capacitor
should be chosen. When running at the minimum cycle
time of 2µs, the input current equals 106µA at V
IN
= 5V,
which amounts to a full‑scale error of 0.5LSB when using
a filter resistor (R
FILTER
) of 4.7Ω. Applications requiring
lower sample rates can tolerate a larger filter resistor for
the same amount of full‑scale error.
C
IN
55pF
R
ON
100Ω
R
SOURCE
V
IN
LTC2302
LTC2306
INPUT
(CH0, CH1
IN
+
, IN
–
)
C1
23026 F02a
R
EQ
1/(f
SMPL
• C
IN
)
V
REF
/2
R
FILTER
I
DC
V
IN
LTC2302
LTC2306
INPUT
(CH0, CH1
IN
+
, IN
–
)
C
FILTER
23026 F02b
+
–
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LTC2302CDD#TRPBF

Mfr. #:
Buy LTC2302CDD#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit -1ch Differential 500ksps SAR ADC with SPI I/F
Lifecycle:
New from this manufacturer.
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