1
®
FN4153.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HA456
120MHz, Low Power, 8x8 Video
Crosspoint Switch
The HA456 is the first 8x8 video crosspoint switch suitable
for high performance video systems. Its high level of
integration significantly reduces component count, board
space, and cost. The crosspoint switch contains a digitally
controlled matrix of 64 fully buffered switches that connect 8
video input signals to any, or all, matrix outputs. Each matrix
output connects to an internal, high-speed (200V/µs), unity
gain buffer capable of driving 400Ω and 5pF to ±2V.
For applications requiring gain or increased drive capability,
the HA456 outputs can be connected directly to two
HFA1412 quad, gain of two video buffers, which are capable
of driving 75Ω loads.
This crosspoint’s true high impedance three-state output
capability, makes it feasible to parallel multiple HA456s and
form larger switch matrices.
Ordering Information
Features
Fully Buffered Inputs and Outputs (A
V
= +1)
Routes Any Input Channel to Any Output Channel
Switches Standard and High Resolution Video Signals
Serial or Parallel Digital Interface
Expandable for Larger Switch Matrices
Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 120MHz
High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 200V/µs
Differential Gain and Phase . . . . . . . . . . . . . .0.05%, 0.05°
Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . . -55dB
Pb-Free Available (RoHS Compliant)
Applications
Professional Video Switching and Routing
Security and Video Editing Systems
Pinout
HA456
(44 LD PLCC)
TOP VIEW
PART
NUMBER
PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
HA456CM HA456CM 0 to +70 44 Ld PLCC N44.65
HA456CMZ
(Note)
HA456CMZ 0 to +70 44 Ld PLCC
(Pb-free)
N44.65
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
2827
123456
262524232221201918
7
8
9
10
11
12
13
14
15
16
17
A0
IN1
NC
IN2
DGND
NC
IN3
DGND
IN4
EDGE/LEVEL
IN5
IN0
A1
A2
D0/SER IN
D1/SER OUT
NC
V+
OUT0
D2
OUT1
D3
V+
IN6
SER/PAR
IN7
V-
NC
WR
LATCH
CE
CE
OUT7
OUT2
V-
OUT3
AGND
OUT4
NC
AGND
OUT5
AGND
OUT6
V+
Data Sheet September 26, 2008
2
FN4153.7
September 26, 2008
HA456 Functional Block Diagram
IN0 IN2 IN3 IN4 IN5 IN6 IN7IN1
(A
V
= 1)
OUTPUT
BUFFERS
OUT0
OUT7
SLAVE REGISTER
MASTER REGISTER
LATCH
EDGE/LEVEL
CE
WR
CE
A0 A1 A2 D2 D3
D0/SER IN
D1/SER OUT
SER/PAR
HA456
8x8
SWITCH
MATRIX
EN0:7
EN0
EN7
HA456
3
FN4153.7
September 26, 2008
Pin Descriptions
NAME FUNCTION
NC No connect. Not internally connected.
D1/SER OUT Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift register) for cascading multiple
HA456s in serial programming mode. Simply connect Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy
chain multiple devices.
D0/SER IN Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift register) for serial programming mode.
A2, A1, A0 Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode.
IN0-IN7 Analog Video Input Lines.
DGND Digital Ground. Connect both DGND pins to AGND.
EDGE/LEVEL
A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin is strapped
high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH
signal. If it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the
master register to the switch state decoders. Strapping EDGE/LEVEL
and LATCH low causes the channel switch to execute on
the WR rising edge (not recommended for serial mode operation).
V+ Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND (see Figure 2).
SER/PAR
A user strapped input that defines whether the serial (SER/PAR = 1) or parallel (SER/PAR = 0) digital programming interface is
being utilized.
V- Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND (see Figure 2).
WR WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In
parallel mode, the Master Register loads with D3:0 (if D3:0 = 0000 through 1000), or the appropriate action is taken
(if D3:0 =1011 through 1111), on the WR rising edge (see Table 1).
LATCH Synchronous Channel Switch Control Input. If EDGE/LEVEL
= 1, data is loaded from the Master Register to the Slave Register
on the rising edge of LATCH. If EDGE/LEVEL
= 0, data is loaded from the Master to the Slave Register while LATCH = 0. In
parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH
or EDGE/LEVEL
. Parallel mode command 1111 executes a software “Latch” (see Table 1).
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
CE Chip Enable. When CE
= 0 and CE = 1, the WR line is enabled.
OUT7-OUT0 Analog Video Outputs.
AGND Analog Ground.
D3 Parallel Data Bit Input D3 when SER/PAR
= 0. D3 is unused with serial programming.
D2 Parallel Data Bit Input D2 when SER/PAR
= 0. D2 is unused with serial programming.
HA456

HA456CMZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog & Digital Crosspoint ICs W/ANNEAL XPOINT 8X8 VID GAIN+1 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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