7
FN4153.7
September 26, 2008
Figure 2 shows a typical application of the HA456 with
HFA1412 quad, gain-of-two buffers at the outputs to drive
75Ω loads. This application shows the HA456 digital-switch
control interface set up in the 7-bit parallel mode. The HA456
uses 7 data lines and 3 control lines (WR, CE
and LATCH).
The input/output information is presented to the chip at A2:0
and D3:0 by a parallel printer port. The data is stored in the
Master Registers on the rising edge of WR. When the
LATCH line goes high, the switch configuration loads into the
Slave Registers, and all 8 outputs reconfigure at the same
time. Each 7-bit word updates only one output at a time.
If several outputs are to be updated, the data is individually
loaded into the Master Registers. Then, a single LATCH
pulse can reconfigure all channels simultaneously.
An IBM compatible PC loads the programming data into the
HA456 via its parallel port (LPT1) using a simple BASIC
program.
TABLE 1. PARALLEL INTERFACE COMMANDS
A2:0 D3:0 ACTION
Selects
Output
Being
Programmed
0000 to 0111 Connect the input defined by D3:0 to the output selected by A2:0. Doesn’t enable a disabled output.
1000 Connect the output selected by A2:0 to GND. Doesn’t enable a disabled output.
1011 Asynchronously disable the single output selected by A2:0, and leave the Master Register unchanged.
1100 Asynchronously enable the single output selected by A2:0, and leave the Master Register unchanged.
Address
Inputs are
Irrelevant for
These
Functions
1101 Asynchronously disable all outputs, and leave the Master Register unchanged.
1110 Asynchronously enable all outputs, and leave the Master Register unchanged.
1111 Send a Software “Latch” pulse to the Slave Register to load it from the Master Register, iff, the LATCH input = 1.
If the LATCH input = 0, then this command is a NOP. The Master Register is unchanged by this command.
1001 or 1010 Do not use these codes in the parallel programming mode. These codes are for serial programming only.
TABLE 2. SERIAL INTERFACE COMMANDS
D3:0 ACTION
0000 to 0111 Connect the output to the input channel defined by D3:0. Doesn’t enable a disabled output.
1000 Connect the output to GND. Doesn’t enable a disabled output.
1001 Enable the output and connect it to GND. The default power-up state is all outputs disabled, so use this code to enable
outputs after power is applied, but before programming the switch configuration.
1010 Disable the output. The output is no longer associated with any input channel; the desired input must be redefined after
re enabling the output.
1011 to 1111 Do not use these codes in the serial programming mode.
TABLE 3. DEFINITION OF DATA AND ADDRESS BIT FUNCTIONS
SER/PAR D3 D2 D1 D0 A2:0 COMMENT
HXXSerial Data
Output
Serial Data Input X 32-Bit Serial Mode
LHParallel Data
Input
Parallel Data
Input
Parallel Data
Input
Output
Address
Parallel Mode; D2:0 define the
command to be executed
LLParallel Data
Input
Parallel Data
Input
Parallel Data
Input
Output
Address
Parallel Mode; D2:0 define the Input
Channel
HA456
8
FN4153.7
September 26, 2008
30
19
2
3
4
5
6
7
8
1
14
17
19
21
15
13
10
8
6
25
24
3
2
42
40
7
5
4
43
41
34
37
35
32
30
28
27
16
18, 29, 44
31, 33, 36
11, 14
22, 38
26
20
7
8
14
3
5
10
12
11
75Ω
1
75Ω
IN 1
IN 2
IN 3
IN 4
OUT1
OUT2
OUT3
OUT4
V+ V-
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
LATCH
WR
D2
D3
A0
A1
A2
D0/SER IN
D1/SER OUT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CE
EDGE/LEVEL
V+
AGND
DGND
V-
CE
SER/PAR
HA456
HFA1412
VIDEO
INPUTS
+5V
-5V
-5V
NOTE: All decoupling capacitors 0.1µF Ceramic (1 per supply pin). For lowest crosstalk, connect unused pins to GND use R
S
to tune the overall
output response.
FIGURE 2. TYPICAL HIGH PERFORMANCE, PARALLEL MODE APPLICATION CIRCUIT (SEE FIGURE 18)
(A
V
=+2)
4
-IN0:3
2, 6 9, 13
18
36
16
33
R
S
R
S
R
S
NC
V
OUT
Waveforms
FIGURE 3. DIGITAL TIMING REQUIREMENTS
VALID DATA
VALID DATA
t
DS
t
WL
t
DH
t
WH
t
L
t
D
A2:0, D3:0
WR
LATCH
(EDGE MODE)
CE
t
CS
t
CH
HA456
9
FN4153.7
September 26, 2008
FIGURE 4. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)
FIGURE 5. SERIAL PROGRAMMING MODE OPERATION (SER/PAR
= 1)
Waveforms (Continued)
DATA (N) DATA (N + 1)
DATA (N + 2)
DATA (N)
DATA (N)
DATA (N)
DATA (N + 1)
DATA (N + 1)
DATA (N + 1)
DATA (N + 2)
WR
LATCH
MASTER REGISTER CONTENTS
SLAVE REGISTER CONTENTS
(EDGE/LEVEL
= 0)
SLAVE REGISTER CONTENTS
(EDGE/LEVEL
= 1)
DATA (N + 2)
DATA (N + 2)
SLAVE REGISTER CONTENTS
(EDGE/LEVEL
= 0)
SLAVE REGISTER CONTENTS
(EDGE/LEVEL
= 1)
WR
LATCH
NEW DATA
NEW DATA
NEW DATA FOR
OUT1 TO OUT6
NEW DATA FOR
OUT0
NEW DATA FOR
OUT7
D1D2D3 D0 D3 D2 D3 D2 D1 D0
t = 0
1st
WRITE
32nd
WRITE
OLD DATA
OLD DATA
SER IN
HA456

HA456CMZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog & Digital Crosspoint ICs W/ANNEAL XPOINT 8X8 VID GAIN+1 44PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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