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LT6220IS5#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LT6220/LT6221/LT6222
13
622012fc
For more information www.linear.com/LT6220/LT6221/LT6222
Typical perForMance characTerisTics
±5V Large-Signal Response ±5V Small-Signal Response Output Overdriven Recovery
applicaTions inForMaTion
Q4
Q18Q17
Q16
Q6
Q3
Q7
Q1
Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2ESDD1
+IN
–IN
V
–
ESDD3ESDD4
V
+
V
+
V
–
R2R1
R3 R4 R5
622012 F01
+
I
2
+
I
3
C2
C
C
V
–
+
C1
BUFFER
AND
OUTPUT BIAS
V
+
V
–
Q19
Q14
Q8
Q13
Q10
Circuit Description
The LT6220/LT6221/LT6222 have an input and output
signal range that covers from the negative power supply
to the positive power supply. Figure 1 depicts a simplified
schematic of the amplifier. The input stage comprises
two differential amplifiers, a PNP stage, Q1/Q2, and an
NPN stage, Q3/Q4, that are active over different ranges
of common mode input voltage. The PNP stage is active
between the negative supply to approximately 1.2V below
the positive supply. As the input voltage moves closer
toward the positive supply, the transistor Q5 will steer the
tail current, I
1
, to the current mirror, Q6/Q7, activating the
NPN differential pair and the PNP pair becomes inactive
for the rest of the input common mode range up to the
positive supply. Also, at the input stage, devices Q17 to
Q19 act to cancel the bias current of the PNP input pair.
When Q1/Q2 are active, the current in Q16 is controlled
to be the same as the current Q1/Q2. Thus, the base cur
-
rent of Q16 is nominally equal to the base current of the
input
devices. The base current of Q16 is then mirrored by
devices Q17-Q19 to
cancel the base current of the input
devices Q1/Q2.
Figure 1. LT6220/LT6221/LT6222 Simplified Schematic Diagram
0V
2V/DIV
200ns/DIV
622012 G38
V
S
= ±5V
A
V
= 1
R
L
= 1k
0V
50mV/DIV
50ns/DIV
622012 G39
V
S
= ±5V
A
V
= 1
R
L
= 1k
0V
0V
V
IN
1V/DIV
V
OUT
2V/DIV
200ns/DIV
622012 G40
V
S
= 5V, 0V
A
V
= 2
R
L
= 1k
LT6220/LT6221/LT6222
14
622012fc
For more information www.linear.com/LT6220/LT6221/LT6222
applicaTions inForMaTion
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail-to-rail construct
the output stage. The capacitors C2 and C3 form the local
feedback loops that lower the output impedance at high
frequency. These devices are fabricated by Linear Tech
-
nology’s proprietar
y
high speed complementary bipolar
process.
Power Dissipation
The LT6222, with four amplifiers, is housed in a small
16-lead SSOP package and typically has a thermal resis
-
tance (θ
JA
) of 135°C/W. It is necessary to ensure that the
die’s junction temperature does not exceed 150°C. The
junction temperature, T
J
, is calculated from the ambi-
ent temperature,
T
A
, power dissipation, P
D
, and thermal
resistance, θ
JA
:
T
J
= T
A
+ (P
D
• θ
JA
)
The power dissipation in the IC is the function of the sup-
ply voltage
, output voltage and the load resistance. For
a
given supply voltage, the worst-case power dissipation
P
D(MAX)
occurs when the maximum supply current and
the output voltage is at half of either supply voltage for a
given load resistance. P
D(MAX)
is given by:
P
D(MAX)
= V
S
•I
S(MAX)
( )
+
V
S
2
2
/ R
L
Example: For an LT6222 in a 16-lead SSOP package
operating on ±5V supplies and driving a 100Ω load, the
worst-case power dissipation is given by:
P
D(MAX)
/Amp = 10 • 1.8mA
( )
+ 2.5
( )
2
/ 10
0
= 0.018+0.0625 = 80.5mW
If all four amplifiers are loaded simultaneously, then the
total power dissipation is 322mW.
The maximum ambient temperature at which the part is
allowed to operate is:
T
A
= T
J
– (P
D(MAX)
• 135°C/W)
= 150°C – (0.322W • 135°C/W) = 106.5°C
Input Offset Voltage
The offset voltage will change depending upon which input
stage is active. The PNP input stage is active from the nega-
tive supply
rail to 1.2V below the positive supply rail, then
the
NPN input stage is activated for the remaining input
range up to the positive supply rail during which the PNP
stage remains inactive. The offset voltage is typically less
than 70µV in the range that the PNP input stage is active.
Input Bias Current
The LT6220/LT6221/LT6222 employ a patent pending
technique to trim the input bias current to less than 150nA
for the input common mode voltage of 0.2V above the
negative supply rail to 1.2V below the positive rail. The
low input offset voltage and low input bias current of the
LT6220/LT6221/LT6222 provide precision performance
especially for high source impedance applications.
Output
The LT6220/LT6221/LT6222 can deliver a large output cur
-
rent, so the short-circuit current limit is set around 50mA
to prevent damage to the device. Attention must be paid to
keep the junction temperature of the IC below the absolute
maximum rating of 150°C (refer to the Power Dissipation
section) when the output is in continuous short circuit.
The output of the amplifier has reverse-biased diodes
connected to each supply. If the output is forced beyond
either supply, unlimited current will flow through these
diodes. If the current is transient and limited to several
hundred milliamperes, no damage will occur to the device.
Overdrive Protection
When the input voltage exceeds the power supplies, two
pair of crossing diodes, D1 to D4, will prevent the output
from reversing polarity. If the input voltage exceeds ei
-
ther power
supply by 700mV, diode D1/D2 or D3/D4 will
turn
on to keep the output at the proper polarity. For the
phase reversal protection to perform properly, the input
current must be limited to less than 5mA. If the amplifier
LT6220/LT6221/LT6222
15
622012fc
For more information www.linear.com/LT6220/LT6221/LT6222
applicaTions inForMaTion
Typical applicaTions
is severely overdriven, an external resistor should be used
to limit the overdriven current.
The LT6220/LT6221/LT6222’s input stages are also pro
-
tected against a large differential input voltage of 1.4V or
higher by a pair of back-to-back diodes, D5/D8, to prevent
the emitter-base breakdown of the input transistors. The
current in these diodes should be limited to less than
10mA when they are active. The worse-case differential
input voltage usually occurs when the input is driven while
the output is shorted to ground in a unity-gain configura
-
tion. In addition, the amplifier is protected against ESD
strikes
up to 3kV on all pins by a pair of protection diodes
on each pin that are connected to the power supplies as
shown in Figure 1.
Capacitive Load
The LT6220/LT6221/LT6222 are optimized for high
bandwidth, low power and precision applications. They
can drive a capacitive load up to 100pF in a unity-gain
configuration and more for higher gain. When driving a
larger capacitive load, a resistor of 10Ω to 50Ω should be
connected between the output and the capacitive load to
avoid ringing or oscillation. The feedback should still
be
taken
from the output so that the resistor will isolate the
capacitive load to ensure stability. Graphs on capacitive
loads show the transient response of the amplifier when
driving capacitive load with specified series resistors.
Feedback Components
When feedback resistors are used to set up gain, care must
be taken to ensure that the pole formed by the feedback
resistors and the total capacitance at the inverting input
does not degrade stability. For instance, the LT6220/
LT6221/LT6222, set up with a noninverting gain of 2, two
5k resistors and a capacitance of 5pF (part plus PC board),
will probably oscillate. The pole is formed at 12.7MHz that
will reduce phase margin by 52 degrees when the crossover
frequency of the amplifier is around 10MHz. A capacitor
of 10pF or higher connecting across the feedback resistor
will eliminate any ringing or oscillation.
Stepped-Gain Photodiode Amplifier
The circuit of Figure 2 is a stepped gain transimpedance
photodiode amplifier. At low signal levels, the circuit has
a high 100kΩ gain, but at high signal levels the circuit
automatically and smoothly changes to a low 3.2kΩ gain.
The benefit of a stepped gain approach is that it maximizes
dynamic range, which is very
useful on limited supplies.
Put
another way, in order to get 100kΩ sensitivity and still
handle a 1mA signal level without resorting to gain reduc
-
tion, the circuit would need a 100V negative voltage supply.
The operation of the circuit is quite simple. At low photodi-
ode currents
(
below 10µA) the output and inverting input
of the op amp will be no more than 1V below ground. The
LT1634 in parallel with R3 and Q2 keep a constant current
though Q2 of about 20µA. R4 maintains quiescent current
through the LT1634 and pulls Q2’s emitter above ground,
so Q1 is reverse biased and no current flows through R2.
So for small signals, the only feedback path is R1 (and
C1) and the circuit is a simple transimpedance amplifier
with 100kΩ gain.
Figure 2. Stepped-Gain Photodiode Amplifier
–
+
I
PD
PHOTODIODE
~4pF
V
S
+
V
S
+
V
S
+
V
S
–
V
S
–
LT6220
R1
100k
R2
3.24k
R3
33k
R4
10k
C1
1pF
C2
30pF
Q1 Q2
12
3 4
PHILIPS
BCV62
LT1634-1.25
V
OUT
V
S
= ±1.5V TO ±5V
622012 F02
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

LT6220IS5#TRPBF

Mfr. #:
Buy LT6220IS5#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers 1x 60MHz, 20V/ s L Pwr, R2R In & Out Pr
Lifecycle:
New from this manufacturer.
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