932S805CGLF Datasheet 932S805CGLF, 932S805CGLFT | P10-P12

ICS932S805C

K8 Clock Chip for Serverworks HT2100 Servers

IDT

K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10

Bytes 11:14 Are Reserved

SMBus Table: CPU/SRC Frequency Control Register

Name Control Function T

e0 1PWD

Bit 7

N Div8 N Divider Prog bit 8 RW X

Bit 6

N Div9 N Divider Prog bit 9 RW X

Bit 5

M Div5 RW X

Bit 4

M Div4 RW X

Bit 3

M Div3 RW X

Bit 2

M Div2 RW X

Bit 1

M Div1 RW X

Bit 0

M Div0 RW X

SMBus Table: CPU/SRC Frequency Control Register

Name Control Function T

e0 1PWD

Bit 7

N Div7 RW X

Bit 6

N Div6 RW X

Bit 5

N Div5 RW X

Bit 4

N Div4 RW X

Bit 3

N Div3 RW X

Bit 2

N Div2 RW X

Bit 1

N Div1 RW X

Bit 0

N Div0 RW X

SMBus Table: CPU/SRC Spread Spectrum Control Register

Name Control Function T

e0 1PWD

Bit 7

SSP7 RW X

Bit 6

SSP6 RW X

Bit 5

SSP5 RW X

Bit 4

SSP4 RW X

Bit 3

SSP3 RW X

Bit 2

SSP2 RW X

Bit 1

SSP1 RW X

Bit 0

SSP0 RW X

te 17

te 16

te 15

Spread Spectrum Programming bit(7:0)

These Spread Spectrum bits

in Byte 17 and 18 will

program the spread

pecentage of CPU and SRC

outputs.

N Divider Programming Byte12 bit(7:0)

and Byte11 bit(7:6)

M Divider Programming

bit (5:0)

The decimal representation

of M and N Divier in Byte 15

and 16 will configure the

CPU VCO frequency.

Default at power up = latch-

in or Byte 0 Rom table. VCO

Frequency = 14.318 x

[NDiv(9:0)+8] / [MDiv(5:0)+2]

The decimal representation

of M and N Divier in Byte 15

and 16 will configure the

CPU VCO frequency.

Default at power up = latch-

in or Byte 0 Rom table. VCO

Frequency = 14.318 x

[NDiv(9:0)+8] / [MDiv(5:0)+2]

ICS932S805C

K8 Clock Chip for Serverworks HT2100 Servers

IDT

K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10

SMBus Table: CPU/SRC Spread Spectrum Control Register

Pin # Name Control Function T

e0 1PWD

Bit 7

Reserved Reserved R - - 0

Bit 6

SSP14 RW X

Bit 5

SSP13 RW X

Bit 4

SSP12 RW X

Bit 3

SSP11 RW X

Bit 2

SSP10 RW X

Bit 1

SSP9 RW X

Bit 0

SSP8 RW X

SMBus Table: SRC Spread Spectrum Control Register

Pin # Name Control Function T

e0 1PWD

Bit 7

Reserved Reserved R - - 0

Bit 6

Reserved Reserved R - - 0

Bit 5

Reserved Reserved R - - 0

Bit 4

Reserved Reserved R - - 0

Bit 3

Reserved Reserved R - - 0

Bit 2

Reserved Reserved R - - 0

Bit 1

Reserved Reserved R - - 0

Bit 0

Reserved Reserved R - - 0

SMBus Table: Programmable Output Divider Register

Pin # Name Control Function T

e0 1PWD

Bit 7

CPUDiv3 RW X

Bit 6

CPUDiv2 RW X

Bit 5

CPUDiv1 RW X

Bit 4

CPUDiv0 RW X

Bit 3

Reserved Reserved R - - 0

Bit 2

Reserved Reserved R - - 0

Bit 1

Reserved Reserved R - - 0

Bit 0

Reserved Reserved R - - 0

SMBus Table: Programmable Output Divider Register

Pin # Name Control Function T

e0 1PWD

Bit 7

33MHzDiv3 RW X

Bit 6

33MHzDiv2 RW X

Bit 5

33MHzDiv1 RW X

Bit 4

33MHzDiv0 RW X

Bit 3

SRC_Div3 RW X

Bit 2

SRC_Div2 RW X

Bit 1

SRC_Div1 RW X

Bit 0

SRC_Div0 RW X

SMBusTable: Reserved Regsiter

Byte 21 is reserved do not write this register!

te 18

te 19

te 20

33MHz Divider Ratio Programming

Bits

33MHz Divider Ratio Table

See CPU Divider Ratios

Table

Spread Spectrum Programming

bit(14:8)

SRC Divider Ratio Table

CPU Divider Ratio Programming Bits

SRC_ Divider Ratio Programming Bits

These Spread Spectrum bits

in Byte 17 and 18 will

program the spread

pecentage of CPU and SRC

outputs.

ICS932S805C

K8 Clock Chip for Serverworks HT2100 Servers

IDT

K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10

Absolute Maximum Ratings

Electrical Characteristics - Input/Supply/Common Output Parameters

= 0 - 70°C; Supply Voltage V

= 3.3 V +/-5%

PARAMETER SYMBOL Conditions MIN TYP MAX UNITS NOTES

Input High Voltage V

3.3 V +/-5% 2 V

+ 0.3 V 1

Input Low Voltage V

3.3 V +/-5% V

- 0.3 0.8 V 1

Input High Current I

= V

-5 5 uA 1

IL1

= 0 V; Inputs with no pull-up

resistors

-5 uA 1

IL2

= 0 V; Inputs with pull-up

resistors

-200 uA 1

Operating Supply Current I

DD3.3OP

Full Active, C

= Full load;

258

350 mA

Operating Current I

DD3.3OP

all outputs driven tbd mA

all diff pairs driven tbd mA

all differential pairs tri-stated tbd mA

Input Frequenc

= 3.3 V 14.318 MHz 3

Pin Inductance

7nH1

Logic Inputs 5 pF 1

Output pin capacitance 6 pF 1

INX

X1 & X2 pins 5 pF 1

Clk Stabilization

1,2

STAB

From V

Power-Up or de-assertion

of PD# to 1st clock

3ms1,2

Modulation Frequenc

Trian

ular Modulation 30 33 kHz 1

SMBus Voltage V

2.7 5.5 V 1

Low-level Output Voltage V

@ I

PULLUP

0.4 V 1

rrent sinking at V

= 0.4 I

PULLUP

4mA1

SCLK/SDATA

Clock/Data Rise Time

RI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000 ns 1

SCLK/SDATA

Clock/Data Fall Time

FI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300 ns 1

Guaranteed by design and characterization, not 100% tested in production.

See timing diagrams for timing requirements.

Input frequenc

should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet

ppm frequenc

accurac

on PLL outputs.

Input Low Current

Powerdown Current I

DD3.3PD

Input Capacitance

Symbol Parameter Min Max Units

VDD_A 3.3V Core Supply Voltage - VDD + 0.5V V

VDD_In

3.3V Logic Input Supply Voltage

GND - 0.5 VDD + 0.5V V

Ts Storage Temperature -65 150 °C

Tambient Ambient Operating Temp 0 70 °C

Tc Case Temperature - 115 °C

ESD prot Input ESD protection human body model 2000 - V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

932S805CGLF

Mfr. #:

Buy 932S805CGLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK

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New from this manufacturer.

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932S805CGLF

932S805CGLF

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