932S805CGLF Datasheet 932S805CGLF, 932S805CGLFT | P7-P9

ICS932S805C

K8 Clock Chip for Serverworks HT2100 Servers

IDT

K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10

SMBus Table: Frequency Select and Spread Control Register

Name Control Function T

e0 1PWD

Bit 7

FS Source

Latched Input or SMBus Frequency

Select

RW Latched Inputs SMBus 0

Bit 6

Spread

Spectrum

Enable

Spread Enable for CPU, SRC and PCI Outputs.

Setting SPREAD_EN pin to '1', forces

Spread ON and overides this bit.

RW OFF ON 0

Bit 5

Reserved Reserved RW Reserved Reserved 0

Bit 4

Reserved Reserved RW Reserved Reserved 0

Bit 3

FS3 Freq Select Bit 3 RW Latched

Bit 2

FS2 Freq Select Bit 2 RW Latched

Bit 1

FS1 Freq Select Bit 1 RW Latched

Bit 0

FS0 Freq Select Bit 0 RW Latched

SMBus Table: Output Control Register

Name Control Function T

e0 1PWD

Bit 7

REF2 Output Enable RW Disable (Low) Enable 1

Bit 6

REF1 Output Enable RW Disable (Low) Enable 1

Bit 5

REF0 Output Enable RW Disable (Low) Enable 1

Bit 4

PCICLK1 Output Enable RW Disable (Low) Enable 1

Bit 3

PCICLK0 Output Enable RW Disable (Low) Enable 1

Bit 2

48MHz_2 Output Enable RW Disable (Low) Enable 1

Bit 1

48MHz_1 Output Enable RW Disable (Low) Enable 1

Bit 0

48MHz_0 Output Enable RW Disable (Low) Enable 1

SMBus Table: Output Control Register

Name Control Function T

e0 1PWD

Bit 7

Reserved Reserved RW Reserved Reserved 0

Bit 6

CPUCLK8(6) RW Disable Enable 1

Bit 5

CPUCLK8(5) RW Disable Enable 1

Bit 4

CPUCLK8(4) RW Disable Enable 1

Bit 3

CPUCLK8(3) RW Disable Enable 1

Bit 2

CPUCLK8(2) RW Disable Enable 1

Bit 1

CPUCLK8(1) RW Disable Enable 1

Bit 0

CPUCLK8(0) RW Disable Enable 1

te 1

te 2

47/46

45/44

59/58

57/56

53/52

51/50

43/42

te 0

Output Enable

When Disabled

CPUCLKT = 0

CPUCLKC = 1

See CPU Frequency Select

Table

ICS932S805C

K8 Clock Chip for Serverworks HT2100 Servers

IDT

K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10

SMBus Table: Output Control Register

Name Control Function T

e0 1PWD

Bit 7

SRCCLK PD SRCCLK Power Down Drive Mode RW Driven Hi-Z 0

Bit 6

Reserved Reserved RW Reserved Reserved 0

Bit 5

SRCCLK5 Output Enable RW Disable (Hi-Z) Enable 1

Bit 4

SRCCLK4 Output Enable RW Disable (Hi-Z) Enable 1

Bit 3

SRCCLK3 Output Enable RW Disable (Hi-Z) Enable 1

Bit 2

SRCCLK2 Output Enable RW Disable (Hi-Z) Enable 1

Bit 1

SRCCLK1 Output Enable RW Disable (Hi-Z) Enable 1

Bit 0

SRCCLK0 Output Enable RW Disable (Hi-Z) Enable 1

SMBus Table: Drive Strength Control Register

Name Control Function T

e0 1PWD

Bit 7

REF2 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 6

REF1 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 5

REF0 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 4

PCICLK1 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 3

PCICLK0 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 2

48MHz_2 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 1

48MHz_1 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 0

48MHz_0 Drive Strength Select RW 1 Load 2 Loads 1

SMBus Table: SRC Frequency Select Register

Name Control Function T

e0 1PWD

Bit 7

25MHz_1 Output Enable RW Disable (Low) Enable 1

Bit 6

25MHz_0 Output Enable RW Disable (Low) Enable 1

Bit 5

25MHz_1 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 4

25MHz_0 Drive Stren

th Select RW 1 Load 2 Loads 1

Bit 3

Reserved Reserved RW Reserved Reserved 0

Bit 2

Reserved Reserved RW Reserved Reserved 0

Bit 1

Reserved Reserved RW Reserved Reserved 0

Bit 0

Reserved Reserved RW Reserved Reserved 0

SMBus Table: Device ID Register

Name Control Function T

e0 1PWD

Bit 7

DevID 7 Device ID MSB R - - 1

Bit 6

DevID 6 Device ID 6 R - - 0

Bit 5

DevID 5 Device ID 5 R - - 0

Bit 4

DevID 4 Device ID4 R - - 0

Bit 3

DevID 3 Device ID3 R - - 0

Bit 2

DevID 2 Device ID2 R - - 1

Bit 1

DevID 1 Device ID1 R - - 0

Bit 0

DevID 0 Device ID LSB R - - 1

te 6

te 3

SRC CLKs

38/37

36/35

34/33

29/30

27/28

25/26

te 4

te 5

ICS932S805C

K8 Clock Chip for Serverworks HT2100 Servers

IDT

K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10

SMBus Table: Vendor ID Register

Name Control Function T

e0 1PWD

Bit 7

RID3 R - - X

Bit 6

RID2 R - - X

Bit 5

RID1 R - - X

Bit 4

RID0

--X

Bit 3

VID3

--0

Bit 2

VID2

--0

Bit 1

VID1

--0

Bit 0

VID0 R - - 1

SMBus Table: Byte Count Register

Name Control Function T

e0 1PWD

Bit 7

BC7 RW 0

Bit 6

BC6 RW 0

Bit 5

BC5 RW 0

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 0

Bit 1

BC1 RW 0

Bit 0

BC0 RW 1

SMBus Table: Reserved Register

Name Control Function T

e0 1PWD

Bit 7

Reserved Reserved RW Reserved Reserved 0

Bit 6

Reserved Reserved RW Reserved Reserved 0

Bit 5

Reserved Reserved RW Reserved Reserved 0

Bit 4

Reserved Reserved RW Reserved Reserved 0

Bit 3

Reserved Reserved RW Reserved Reserved 0

Bit 2

Reserved Reserved RW Reserved Reserved 0

Bit 1

Reserved Reserved RW Reserved Reserved 0

Bit 0

Reserved Reserved RW Reserved Reserved 0

SMBus Table: M/N Programming Enable

Name Control Function T

e0 1PWD

Bit 7

M/N_EN CPU PLL M/N Pro

rammin

Enable RW Disable Enable 0

Bit 6

Reserved Reserved RW - - 0

Bit 5

Reserved Reserved RW - - 0

Bit 4

Reserved Reserved RW - - 0

Bit 3

Reserved Reserved RW - - 0

Bit 2

Reserved Reserved RW - - 0

Bit 1

Reserved Reserved RW - - 0

Bit 0

Reserved Reserved RW - - 0

te 1

te 8

te 7

te 9

Writing to this register will

configure how many bytes

will be read back, default is

9 bytes.

Revision ID

VENDOR ID

(0001 = ICS)

Byte Count Programming b(7:0)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

932S805CGLF

Mfr. #:

Buy 932S805CGLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK

Lifecycle:

New from this manufacturer.

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932S805CGLF

932S805CGLF

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