DOC#: SP-AP-0014 (Rev. 0.2) Page 6 of 13
OE[3:0] Assertion
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 clocks of the
internal reference clock with all differential outputs resuming
simultaneously. All stopped differential outputs must be driven
HIGH within 10 ns of OE deassertion to a voltage greater than
200 mV.
OE[3:0] Deassertion
The impact of deasserting the OE pins is that all SRC outputs
that are set in the control registers to stoppable via deassertion
of OE are to be stopped after their next transition. The final
state of all stopped SRC clocks is Low/Low.
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# has been sampled LOW by the internal reference
clock all differential clocks will be stopped in a glitch-free
mannter to the LOW-LOW state within their next two consec-
utive rising edges.
PD# Deassertion
The power up latency will be less than 2ms for crystal input
reference and less than 8ms for differential input reference
clock. This is the delay from the power supply reaching the
minimum value specified in the datasheet, until the time that
the part is ready to sample any latched inputs on the first rising
edge of CLKPWRGD.
After the first rising edge on the CKPWRGD this pin becmoes
PD#. After a valid rising edge on CKPWRGD/PD# pin, a time
of not more than 1.8ms is allowed for the clock device’s
internal PLL’s to power up and lock. After this time, all outputs
are enabled in a glitch-free manner within a few clock cycles
of each clock.
.
.
.
7 0 R/W BC7 Byte count register for block read operation.
The default value for Byte count is 7.
In order to read beyond Byte 7, the user should change the byte
count limit.to or beyond the byte that is desired to be read.
6 0 R/W BC6
5 0 R/W BC5
4 0 R/W BC4
3 0 R/W BC3
2 1 R/W BC2
1 1 R/W BC1
0 1 R/W BC0
Byte 4: Control Register 4
Byte 5: Control Register 5
Bit @Pup Type Name Description
7 1 R/W RESERVED RESERVED
6 1 R/W SRC_AMP2 SRC amplitude adjustment
000= 300mV, 001=400mV, 010=500mV, 011= 600mV
100= 700mV, 101=800mV, 110=900mV, 111= 1000mV
50R/W SRC_AMP1
41R/W SRC_AMP0
3 1 R/W RESERVED RESERVED
2 0 R/W RESERVED RESERVED
1 0 R/W RESERVED RESERVED
0 0 R/W RESERVED RESERVED
