1. General description
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals.
They are capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T
is defined as the
input hysteresis voltage V
H
.
2. Features
n Wide operating voltage: 1.0 V to 5.5 V
n Optimized for low voltage applications: 1.0 V to 3.6 V
n Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
n Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
n Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
n Multiple package options
n Specified from 40 °Cto+85°C and from 40 °C to +125 °C
3. Applications
n Wave and pulse shapers for highly noisy environments
n Astable multivibrators
n Monostable multivibrators
74LV132
Quad 2-input NAND Schmitt trigger
Rev. 05 — 2 July 2009 Product data sheet
74LV132_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 2 July 2009 2 of 17
NXP Semiconductors
74LV132
Quad 2-input NAND Schmitt trigger
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV132N 40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV132D 40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV132DB 40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV132PW 40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV132BQ 40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mna407
1A
1Y
1
3
1B
2
2A
2Y
4
6
2B
5
3A
3Y
9
8
3B
10
4A
4Y
12
11
4B
13
2
3
&
1
5
6
&
4
10
8
&
9
mna408
13
11
&
12
mna409
A
Y
B
74LV132_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 2 July 2009 3 of 17
NXP Semiconductors
74LV132
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It cannot be
used as a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
132
1A V
CC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
001aac203
1
2
3
4
5
6
7 8
10
9
12
11
14
13
001aah099
74LV132
Transparent top view
V
CC
(1)
2Y 3A
2B 3B
2A 4Y
1Y 4A
1B 4B
GND
3Y
1A
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1A 1 data input
1B 2 data input
1Y 3 data output
2A 4 data input
2B 5 data input
2Y 6 data output
GND 7 ground (0 V)
3Y 8 data output
3A 9 data input
3B 10 data input
4Y 11 data output
4A 12 data input
4B 13 data input
V
CC
14 supply voltage

74LV132N,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Logic Gates QUAD 2-INPUT NAND
Lifecycle:
New from this manufacturer.
Delivery:
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