© 2005 Microchip Technology Inc. DS80227B-page 3
PIC18F2X1X/4X1X
6. Module: Timing Diagrams and
Specifications
Table 25-6: External Clock Timing Requirements
(page 333), has been revised (changes and
additions are shown in bold text).
TABLE 25-6: EXTERNAL CLOCK TIMING REQUIREMENTS
7. Module: EUSART
The RX pin sampling information in Section 17.1.2
“Sampling” has changed. This section now reads
as follows:
17.1.2 SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin when SYNC is clear or
when BRG16 and BRGH are both not set.
The data on the RX pin is sampled once when SYNC is
set or when BRGH16 and BRGH are both set.
8. Module: MSSP
In Section 16.3.2 “Operation”, the following note
has been added:
9. Module: QFN
In the QFN pin diagrams on pages 3 and 4, and in
Table 1-3: PIC18F2410/2510/2515/2610 Pinout I/O
Descriptions, the following note has been added:
Note: It is recommended to connect the bottom
pad of QFN package parts to V
SS.
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 1 MHz XT, RC Oscillator mode
DC 25 MHz HS Oscillator mode
DC 31.25 kHz LP Oscillator mode
DC 40 MHz EC Oscillator mode
Oscillator Frequency
(1)
DC 4 MHz RC Oscillator mode
0.1 4 MHz XT Oscillator mode
4 25 MHz HS Oscillator mode
4 10 MHz HS + PLL Oscillator mode
5 200 kHz LP Oscillator mode
1T
OSC External CLKI Period
(1)
1000 — ns XT, RC Oscillator mode
40 — ns HS Oscillator mode
32 — μs LP Oscillator mode
25 — ns EC Oscillator mode
Oscillator Period
(1)
250 — ns RC Oscillator mode
250 1 μs XT Oscillator mode
40 250 ns HS Oscillator mode
100 250 ns HS + PLL Oscillator mode
5 200 μs LP Oscillator mode
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
Note: The SSPBUF register cannot be used with
read-modify-write instructions, such as
BCF, BTFSC, COMF, etc.
