4
ICS9179B-01
Serial Configuration Command Bitmaps
Byte 0: SDRAM Clock Register
A. For the clock generator to be addressed by an I
2
C controller, the following address must be sent as a start
sequence, with an acknowledge bit between each byte.
B. The clock generator is a slave/receiver I
2
C component. It can "read back "(in Philips I
2
C protocol) the data stored
in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet
the Intel SMB PIIX4 protocol.
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F. To simplify the clock generator I
2
C interface, the protocol is set to use only block writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
G. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H. At power-on, all registers are set to a default condition. Bytes 0 through 2 default to a 1 (Enabled output state).
General I
2
C serial interface information
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Then Byte 0, 1, 2, etc in
sequence until STOP.
Byte 0, 1, 2, etc in sequence until STOP.
Note: PWD = Power-Up Default
