
8
ICS9179B-01
General Layout Precautions:
1) Use a ground plane on the top
layer of the PCB in all areas not
used by traces.
2) Make all power traces and vias as
wide as possible to lower
inductance.
Notes:
1 All clock outputs should have
series terminating resistor. Not
shown in all places to improve
readibility of diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
Capacitor Values:
All unmarked capacitors are 0.01µF ceramic