70V9179L9PF Datasheet 70V9179L7PFG, 70V9179L9PF8, 70V9179L7PF8 | P1-P3

JANUARY 2014

DSC-4860/5

1

Functional Block Diagram

Features:

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

◆

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

– Industrial: 9ns (max.)

◆

Low-power operation

– IDT70V9179L

Active: 500mW (typ.)

Standby: 1.5mW (typ.)

◆

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

◆

Dual chip enables allow for depth expansion without

additional logic

◆

Counter enable and reset features

◆

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 12ns cycle time, 83MHz operation in Pipelined output mode

◆

LVTTL- compatible, single 3.3V (±0.3V) power supply

◆

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Available in a 100-pin Thin Quad Flatpack (TQFP)

◆

Green parts available, see ordering information

IDT70V9179L

HIGH-SPEED 3.3V 32K x 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

R/WR

OER

CE0R

CE1R

FT/PIPER

0

1

0/1

I/O

Control

MEMORY

ARRAY

Counter/

Address

Reg.

I/O

Control

4860 drw 01

A14R

A0R

CLKR

ADSR

CNTENR

CNTRSTR

A0L

CLKL

ADSL

A14L

CNTENL

CNTRSTL

Counter/

Address

Reg.

R/W

L

CE0L

OEL

CE1L

I/O0L - I/O8L

I/O0R - I/O8R

1

0/1

0

,

1

0/1

0

0/1

1

0

FT/PIPEL

6.42

IDT70V9179L

High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

2

Description:

The IDT70V9179 is a high-speed 64/32K x 9 bit synchronous Dual

Port RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on control,

data, and address inputs provide minimal setup and hold times. The timing

latitude provided by this approach allows systems to be designed with very

short cycle times.

Pin Configuration

(1,2,3)

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

With an input data register, the IDT70V9179 has been optimized for

applications having unidirectional or bidirectional data flow in bursts. An

automatic power down feature, controlled by CE0 and CE1, permits the

on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using CMOS high-performance technology, these devices

typically operate on only 500mW of power.

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

Vss

FT/PIPE

R

OE

R

R/W

R

CNTRST

R

CE

1R

CE

0R

NC

Vss

A

12R

A

13R

A

11R

A

10R

A

9R

A

8R

A

7R

NC

A

14R

NC

4860 drw 02_79

NC

FT/PIPE

L

OE

L

R/W

L

CNTRST

L

CE

1L

CE

0L

NC

V

DD

A

14L

A

13L

A

8L

A

7L

NC

A

12L

A

11L

A

10L

A

9L

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

0R

I/O

0L

I/O

1L

Vss

I/O

2L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

3L

I/O

1R

I/O

7R

I/O

8L

I/O

8R

A

6R

A

5R

A

4R

A

3R

A

2R

A

1R

A

0R

CNTEN

R

CLK

R

ADS

R

ADS

L

CLK

L

CNTEN

L

A

0L

A

2L

A

3L

A

5L

A

6L

A

1L

A

4L

NC

V

DD

Vss

V

DD

Vss

NC

70V9179PF

PN100

(4)

100-Pin TQFP

Top View

(5)

NC

,

12/16/13

6.42

IDT70V9179L

High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

3

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

Truth Table I—Read/Write and Enable Control

(1,2,3)

Pin Names

Left Port Right Port Names

CE

0L,

CE

1L

CE

0R,

CE

1R

Chip Enables

R/W

L

R/W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

- A

14L

A

0R

- A

14R

Address

I/O

0L

- I/O

8L

I/O

0R

- I/O

8R

Data Input/Output

CLK

L

CLK

R

Clock

ADS

L

ADS

R

Address Strobe Enable

CNTEN

L

CNTEN

R

Counter Enable

CNTRST

L

CNTRST

R

Counter Reset

FT/PIPE

L

FT/PIPE

R

Flow-Through / Pipeline

V

DD

Power (3.3V)

V

SS

Ground (0V)

4860 tbl 01

OE

CLK

CE

0

CE

1

R/W I/O

0-8

MODE

X

↑

H X X High-Z Deselected–Power Down

X

↑

X L X High-Z Deselected–Power Down

X

↑

LHL DATA

IN

Write

L

↑

LHH DATA

OUT

Read

H X L H X High-Z Outputs Disabled

4860 tbl 02

Truth Table II—Address Counter Control

(1,2,3)

External

Address

Internal

Address

Used CLK

ADS CNTEN CNTRST

I/O

(3)

MODE

An X An

↑

L

(4)

XHD

I/O

(n) External Address Used

XAnAn + 1

↑

H L

(5)

HD

I/O

(n+1) Counter Enabled—Internal Address generation

X An + 1 An + 1

↑

HH HD

I/O

(n+1) External Address Blocked—Counter disabled (An + 1 reused)

XXA

0

↑

XX L

(4)

D

I/O

(0) Counter Reset to Address 0

4860 tbl 03

NOTE:

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE0 and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other signals including CE0 and CE1.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

1. LB and UB are single buffered regardless of state of FT/PIPE.

2. CEo and CE1 are single buffered when FT/PIPE = VIL,

CEo and CE1 are double buffered when FT/PIPE = VIH,

i.e. the signals take two cycles to deselect.

70V9179L9PF

70V9179L9PF

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