OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

70V9179L9PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
Timing Waveform with Port-to-Port Flow-Through Read
(4,5,7)
DATAIN "A"
CLK "B"
R/W "B"
ADDRESS "A"
R/W "A"
CLK "A"
ADDRESS "B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
tCWDD
tCD1
tDC
DATAOUT "B"
4860 drw 09
VALID
VALID
tSW tHW
tSA tHA
tSD tHD
tHW
tCD1
tCCS
tDC
tSA
tSW
tHA
(6)
(6)
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9179 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42
IDT70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)
(3)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An An +1 An + 2 An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
4860 drw 10
Qn
Qn + 3
DATA
OUT
CE
1
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ NOP READ
t
SD
t
HD
(4)
(2)
(1)
(1)
t
SW
t
HW
WRITE
(5)
R/
W
ADDRESS
An An +1 An + 2 An + 3
An + 4
An + 5
DATA
IN
Dn + 3
Dn + 2
CE
0
CLK
4860 drw 11
DATA
OUT
Qn
Qn + 4
CE
1
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
(1)
t
CD2
t
OHZ
(1)
t
CD2
t
SD
t
HD
READ WRITE READ
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
(4)
(2)
t
SW
t
HW
6.42
IDT70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)
(3)
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)
(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/
W
ADDRESS
An
An +1 An + 2 An + 2
An + 3
An + 4
DATA
IN
Dn + 2
CE
0
CLK
4860 drw 12
Qn
DATA
OUT
CE
1
t
CD1
Qn + 1
t
CH1
t
CL1
t
CYC1
t
SD
t
HD
t
CD1
t
CD1
t
DC
t
CKHZ
Qn + 3
t
CD1
t
DC
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
READ
NOP
READ
t
CKLZ
(4)
(2)
(1) (1)
t
SW
t
HW
WRITE
(5)
R/
W
ADDRESS
An
An +1 An + 2 An + 3
An + 4
An + 5
(4)
DATA
IN
Dn + 2
CE
0
CLK
4860 drw 13
Qn
DATA
OUT
CE
1
t
CD1
t
CH1
t
CL1
t
CYC1
t
SD
t
HD
t
CD1
t
DC
Qn + 4
t
CD1
t
DC
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
READ WRITE READ
t
CKLZ
(2)
Dn + 3
t
OHZ
(1)
(1)
t
SW
t
HW
OE
t
OE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V9179L9PF

Mfr. #:
Buy 70V9179L9PF
Manufacturer:
IDT
Description:
SRAM 32K X 9
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet