6.42
IDT70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Capacitance
(1)
(TA = +25°C, f = 1.0MHZ)
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under DC Bias. NO AC Conditions. Chip Deselected.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Grade
Ambient
Temperature
(2)
GND V
DD
Commercial 0
O
C to +70
O
C0V3.3V
+
0.3V
Industrial -40
O
C to +85
O
C0V 3.3V
+
0.3V
4860 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage 2.0V
____
V
CC
+0.3V
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.8 V
4860 tbl 05
Symbol Rating Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6 V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
T
JN
Junction
Temperature
+150
o
C
I
OUT
DC Output Current 50 mA
4860 tbl 06
Symbol Parameter Conditions
(2 )
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
(3 )
Output Capacitance V
OUT
= 3dV 10 pF
4860 tbl 07
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
NOTE:
1. At VDD < 2.0V input leakages are undefined.
Symbol Parameter Test Conditions
70V9179L
UnitMin. Max.
|I
LI
| Input Leakage Current
(1)
V
DD
= 3.6V, V
IN
= 0V to V
DD
___
A
|I
LO
| Output Leakage Current
CE = V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DD
___
A
V
OL
Output Low Voltage I
OL
= +4mA
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
V
4860 tbl 08_79
6.42
IDT70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(3)
(VDD = 3.3V ± 0.3V)
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
70V9179L7
Com'l Only
70V9179L9
Com'l & Ind
70V9179L12
Com'l Only
Symbol Parameter Test Condition Version Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
CC
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
COM'L L 200 310 180 260 150 230
mA
IND L
____ ____
180 280
____ ____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
= CE
R
= V
IH
f = f
MAX
(1)
COM'L L 65 130 50 100 40 80
mA
IND L
____ ____
50 120
____ ____
I
SB2
Standby
Current (One
Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs
Disabled, f=f
MAX
(1)
COM'L L 140 245 110 190 100 175
mA
IND L
____ ____
110 205
____ ____
I
SB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CE
L
and
CE
R
> V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
COM'LL0.430.430.43
mA
IND L
____ ____
0.4 6
____ ____
I
SB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, Active Port,
Outputs Disabled, f = f
MAX
(1)
COM'L L 130 235 100 180 90 165
mA
IND L
____ ____
100 195
____ ____
4860 tbl 09_79
6.42
IDT70V9179L
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
AC Test Conditions
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
4860 drw 04
590Ω
30pF
435Ω
3.3V
DATA
OUT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
4860 drw 03
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1, 2, and 3
4860 tbl 10
1
2
3
4
5
6
7
8
20 40 100 60 80 120 140 160 180 200
tCD
1
,
tCD2
(Typical, ns)
Capacitance (pF)
4860 drw 05
-1
0
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance

70V9179L9PFI8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 32K X 9K
Lifecycle:
New from this manufacturer.
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