Dual Full-Bridge DMOS
PWM Motor Driver
A4954
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Device Operation
The A4954 is designed to operate two DC motors. The output
drivers are all low-R
DS(on)
, N-channel DMOS drivers that feature
internal synchronous rectification to reduce power dissipation.
The current in each of the two output full bridges is regulated
with fixed off-time pulse width modulated (PWM) control cir-
cuitry. The IN1-IN2 and IN3-IN4 inputs allow two-wire control
for each bridge.
Protection circuitry includes internal thermal shutdown, and pro-
tection against shorted loads, or against output shorts to ground
or supply. Undervoltage lockout prevents damage by keeping the
outputs off until the driver has enough voltage to operate nor-
mally.
Standby Mode
Low Power Standby mode is activated when all four input (INx)
pins are low for longer than 1 ms. Low Power Standby mode
disables most of the internal circuitry, including the charge pump
and the regulator. When the A4954 is coming out of standby
mode, the charge pump should be allowed to reach its regulated
voltage (a maximum delay of 200 s) before any PWM com-
mands are issued to the device.
Internal PWM Current Control
Initially, a diagonal pair of source and sink FET outputs are
enabled and current flows through the motor winding and the
optional external current sense resistor, R
Sx
. When the voltage
across R
Sx
equals the comparator trip value, then the current
sense comparator resets the PWM latch. The latch then turns off
the sink and source FETs (Mixed Decay mode).
V
REF
The maximum value of current limiting is set by the selection
of R
Sx
and the voltage at the VREFx pin in each channel. The
transconductance function is approximated by the maximum
value of current limiting, I
TripMAX
(A), which is set by:
I
TripMAX
=
A
V
R
S
V
REF
where V
REF
is the input voltage on the VREFx pin (V) and R
S
is
the resistance of the sense resistor () on the corresponding LSSx
terminal.
Overcurrent Protection
A current monitor will protect the IC from damage due to output
shorts. If a short is detected, the IC will latch the fault and dis-
able the outputs. Each channel has independent OCP protection.
The fault latch can only be cleared by coming out of Low Power
Standby mode or by cycling the power to VBB. During OCP
events, Absolute Maximum Ratings may be exceeded for a short
period of time before the device latches.
Shutdown
If the die temperature increases to approximately 160°C, the full
bridge outputs will be disabled until the internal temperature falls
below a hysteresis, T
TSDhys
, of 15°C. Internal UVLO is present
on VBB to prevent the output drivers from turning-on below the
UVLO threshold.
Braking
The braking function is implemented by driving the device in
Slow Decay mode, which is done by applying a logic high to both
inputs of both channels, after a bridge-enable Chop command
(see PWM Control Truth Table). Because it is possible to drive
current in both directions through the DMOS switches, this con-
figuration effectively shorts-out the motor-generated BEMF, as
long as the Chop command is asserted. The maximum current can
be approximated by V
BEMF
/ R
L
. Care should be taken to ensure
that the maximum ratings of the device are not exceeded in worse
case braking situations: high speed and high-inertia loads.
