2002 Nov 22 12
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
9 L3-BUS DESCRIPTION
9.1 General
The UDA1352TS has an L3-bus microcontroller interface
and all the digital sound processing features and various
system settings can be controlled by a microcontroller.
The controllable settings are:
• Restoring L3-bus default values
• Power-on
• Selection of filter mode and settings of treble and bass
boost
• Volume settings left and right
• Selection of soft mute via cosine roll-off and bypass of
auto mute.
The readable settings are:
• Mute status of interpolator
• PLL locked
• SPDIF input signal locked
• Audio sample frequency
• Valid PCM data detected
• Pre-emphasis of the IEC 60958 input signal
• Accuracy of the clock.
The exchange of data and control information between the
microcontroller and the UDA1352TS is LSB first and is
accomplished through the serial hardware L3-bus
interface comprising the following pins:
• L3DATA: data line
• L3MODE: mode line
• L3CLOCK: clock line.
The L3-bus format has two modes of operation:
• Address mode
• Data transfer mode.
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.5).
The data transfer mode is characterized by L3MODE
being HIGH and is used to transfer one or more bytes
representing a register address, instruction or data.
Basically, two types of data transfers can be defined:
• Write action: data transfer to the device
• Read action: data transfer from the device.
Remark: when the device is powered-up, at least one
L3CLOCK pulse must be given to the L3-bus interface to
wake-up the interface before starting sending to the device
(see Fig.5). This is only needed once after the device is
powered-up.
9.2 Device addressing
The device address consists of 1 byte with:
• Data Operating Mode (DOM) bits 0 and 1 representing
the type of data transfer (see Table 5)
• Address bits 2 to 7 representing a 6-bit device address.
The bits 2 and 3 of the address can be selected via the
external pins DA0 and DA1, which allows up to
4 UDA1352TS devices to be independently controlled in
a single application.
The primary address of the UDA1352TS is ‘001000’ (LSB
to MSB) and the default address is ‘011000’.
Table 5 Selection of data transfer
9.3 Register addressing
After sending the device address (including DOM bits),
indicating whether the information is to be read or written,
one data byte is sent using bit 0 to indicate whether the
information will be read or written and bits 1 to 7 for the
destination register address.
Basically, there are three methods for register addressing:
1. Addressing for write data: bit 0 is logic 0 indicating a
write action to the destination register, followed by bits
1 to 7 indicating the register address (see Fig.5)
2. Addressing for prepare read: bit 0 is logic 1, indicating
that data will be read from the register (see Fig.6)
3. Addressing for data read action. Here, the device
returns a register address prior to sending data from
that register. When bit 0 is logic 0, the register address
is valid; when bit 0 is logic 1, the register address is
invalid.
DOM
TRANSFER
BIT 0 BIT 1
0 0 not used
1 0 not used
0 1 write data or prepare read
11read data
