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FS6128-04G-XTD

P1-P3P4-P6
©2008 SCILLC. All rights reserved. Publication Order Number:
May 2008 – Rev. 2 FS6128-04/D
FS6128-04
PLL Clock Generator IC with VXCO
1.0 Key Features
• Phase-locked loop (PLL) device synthesizes output clock frequency from crystal oscillator or external reference clock
• On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning
• Typically used for generation of MPEG-2 decoder clock
• 3.3V supply voltage
• Very low phase noise PLL
• Use with “pullable” 14pF crystals – no external padding capacitors required
• Small circuit board footprint (8-pin 0.150” SOIC)
• Custom frequency selections available - contact your local ON Semiconductor sales representative for more information
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6128 is circuitry that implements a voltage-controlled crystal oscillator (VCXO) when an external resonator
(nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency
matching requirements, such as digital satellite receivers.
A high-resolution phase-locked loop generates an output clock (CLK) through a post-divider. The CLK frequency is ratiometrically
derived from the VCXO frequency. The locking of the CLK frequency to other system reference frequencies can eliminate unpredictable
artifacts in video systems and reduce electromagnetic interference (EMI) due to frequency harmonic stacking.
Figure 1: Pin Configuration
FS6128-04
Table 1: Crystal / Output Frequencies
Device f
XIN
(MHz) CLK (MHz)
FS128-04 13.500 27.000
Note: Contact ON Semiconductor for custom PLL frequencies.
Figure 2: Block Diagram
Table 2: Pin Descriptions
Pin Type Name Description
1 AI XIN VCXO feedback
2 P VDD Power supply (+3.3V)
3 AI XTUNE VCXO tune
4 P VSS Ground
5 DO CLK Clock output
6 - n/c No connection
7 DO VSS Ground
8 AO XOUT VCXO drive
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input With Internal Pull-Up; DI
D
= Input With Internal Pull-Down; DIO = Digital
Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low Pin
3.0 Functional Block Diagram
3.1 Voltage-Controlled Crystal Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6128 system components. Loading capacitance for
the crystal is internal to the FS6128. No external components (other than the resonator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The value of this voltage
controls the effective capacitance presented to the crystal. The actual amount that this load capacitance change will alter the oscillator
frequency depends on the characteristics of the crystal as well as the oscillator circuit itself.
It is important that the crystal load capacitance is specified correctly to “center” the tuning range. See Table 5.
Rev. 2 | Page 2 of 6 | www.onsemi.com
FS6128-04
A simple formula to obtain the “pulling” capability of a crystal oscillator is:
where:
C
0 = the shunt (or holder) capacitance of the crystal
C
1 = the motional capacitance of the crystal
C
L1 and CL2 = the two extremes (minimum and maximum) of the applied load capacitance presented by the FS6128.
EXAMPLE: A crystal with the following parameters is used: C1 = 0.025pF and C0 = 6pF. Using the minimum and maximum
C
L1 = 10pF, and CL2 = 20pF, the tuning range (peak-to-peak) is:
3.2 Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase locked loop architecture. The PLL multiplies the reference oscillator frequency to
the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise
specified).
4.0 Electrical Specifications
Table 3: Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Supply voltage (V
ss
= ground) V
DD
V
SS
– 0.5 7 V
Input voltage, DC V
I
V
SS
– 0.5 V
DD
+ 0.5 V
Output voltage, DC V
O
V
SS
– 0.5 V
DD
+ 0.5 V
Input clamp current, DC (V
I
< 0 or V
I
> V
DD
) I
IK
-50 50 mA
Output clamp current, DC (V
I
< 0 or V
I
> V
DD
) I
OK
-50 50 mA
Storage temperature range (non-condensing) T
S
-65 150 °C
Ambient temperature range, under bias T
A
-55 125 °C
Junction temperature T
J
125 °C
Re-flow solder profile Per IPC/JEDEC J-STD-020B
Input static discharge voltage protection (MLD-STD 883E, Method 3015.7) 2 kv
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress
rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied.
Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high energy
electrostatic discharge.
Table 4: Operating Conditions
Parameter Symbol Conditions/Descriptions Min. Typ. Max. Units
Supply voltage V
DD
3.3V ± 10% 3.0 3.3 3.6 V
Ambient operating temperature range T
A
0 70 °C
Crystal resonator frequency f
XTAL
Functional mode 12 13.5 18 MHz
Rev. 2 | Page 3 of 6 | www.onsemi.com
P1-P3P4-P6

FS6128-04G-XTD

Mfr. #:
Buy FS6128-04G-XTD
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products VCXO CLOCK 27MHZ OUTPUT
Lifecycle:
New from this manufacturer.
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