FS6128-04
Table 5: DC Electrical Specifications
Parameter Symbol Conditions/Descriptions Min. Typ. Max. Units
Overall
Supply current, dynamic, with loaded outputs I
DD
f
XAL
= 13.5MHz; CL = 10pF; VDD = 3.6V 30 mA
Supply current, static I
DD
XIN = 0V; VDD = 3.6V 3 mA
Voltage-Controlled Crystal Oscillator (contact factory for approved crystal sources or other application assistance)
Crystal loading capacitance at center tuning
voltage
C
L(xtal)
Order crystal for this capacitance
(parallel load) at desired center
frequency
14
pF
Crystal resonator motional capacitance C
1
Specified motional capacitance of the
crystal will affect pullability (see text)
25
fF
XTUNE effective range 0 3 V
Synthesized load capacitance min. C
L1
@V(XTUNE) = minimum value 10 pF
Synthesized load capacitance max. C
L2
@V(XTUNE) = maximum value 20 pF
VCXO tuning range
f
XTAL
= 13.5MHz; C
L(xtal)
= 14pF; C
1
(xtal)
= 25fF (peak-to-peak)
300
ppm
VCXO tuning characteristic
Note: positive change of XTUNE =
positive change of VCXO frequency
150
ppm/V
Crystal drive level R
XTAL
= 20Ω; C
L
= 20pF 200 μW
Clock Output (CLK)
High-level output source current* I
OH
V
O
= 2.0V -40 mA
Low-level output sink current* I
OL
V
O
= 0.4V 17 mA
Output impedance*
Z
OH
Z
OL
V
O
= 0.1V
DD
; output driving high
V
O
= 0.1V
DD
; output driving low
25
25
Ω
Short circuit source current* I
OSH
V
O
= 0V; shorted for 30s, max. -55 mA
Short circuit sink current* I
OSL
V
O
= 3.3V; shorted for 30s, max. 55 mA
Note: Unless otherwise stated V
DD
= 3.3V ±10% no load on any output and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an
asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization
data are ±3σ from typical. Negative currents indicate current flows out of the device.
Table 6: AC Timing Specifications
Parameter Symbol Conditions/Descriptions Min. Typ. Max. Units
Overall
VCXO stabilization time* t
VCXOSTB
From power valid 10 ms
PLL stabilization time* t
PLLSTB
From VCXO stable 100 μs
Synthesis error (Unless otherwise noted in frequency table) 0 ppm
Clock Output (CLK)
Duty cycle*
Ratio of high pulse width (as measured from rising edge to next
falling edge at V
DD
/2) to one clock period
45
55 %
Jitter, period (peak-peak)*
t
j(ΔP)
From rising edge to next rising edge at V
DD
/2, CL = 10pF 200 ps 200 ps
Jitter, long term (σγ(τ)
t
j(LT)
From 0-500μs at V
DD
/2, CL = 10pF compared to ideal clock source 100 ps
Rise time* t
r
V
DD
= 3.3V; V
O
= 0.3V to 3.0V; C
L
= 10pF 1.7 ns
Fall time* t
f
V
DD
= 3.3V; V
O
= 3.0V to 0.3V; C
L
= 10pF 1.7 ns
Note: Unless otherwise stated, V
DD
= 3.3V ±10%, no load on any output, and ambient temperature range T
A
= 0°C to 70°C. Parameters denoted with an
asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization
data are ±3σ from typical.
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