I
2
C Denitions
The following terminology is commonly used to describe
I
2
C data transfers. The timing references are defined in
Figure 43.
Bus Idle or Not Busy
Both SDA and SCL are inactive and in their logic-high
states.
START Condition
To initiate communication with a slave, the master must
generate a START condition. A START condition is
defined as a change in state of SDA from high to low while
SCL remains high.
STOP Condition
To end communication with a slave, the master must
generate a STOP condition. A STOP condition is defined
as a change in state of SDA from low to high while SCL
remains high.
Repeated START Condition
Repeated STARTs are commonly used for read accesses
after having specified a memory address to read from in
a preceding write access. The master can use a repeated
START condition at the end of a data transfer to immedi-
ately initiate a new data transfer following the current one.
A repeated START condition is generated the same way
as a normal START condition, but without leaving the bus
idle after a STOP condition.
Data Valid
With the exception of the START and STOP condition,
transitions of SDA can occur only during the low state of
SCL. The data on SDA must remain valid and unchanged
during the entire high pulse of SCL plus the required
setup and hold time (t
HD:DAT
after the falling edge of SCL
and t
SU:DAT
before the rising edge of SCL; see Figure
43). There is one clock pulse per bit of data. Data is
shifted into the receiving device during the rising edge of
the SCL pulse.
When finished with writing, the master must release the
SDA line for a sufficient amount of setup time (minimum
t
SU:DAT
+ t
R
in Figure 43) before the next rising edge of
SCL to start reading. The slave shifts out each data bit
on SDA at the falling edge of the previous SCL pulse and
the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, includ-
ing those needed to read from a slave.
Figure 43: I
2
C Timing Diagram
SDA
SCL
STOP START
REPEATED
START
SPIKE
SUPPRESSION
t
BUF
t
HD:STA
t
R
t
HD:DAT
t
F
t
HIGH
t
SU:DAT
t
HD:STA
t
SU:STA
t
SP
t
SU:STO
t
LOW
DS2476 DeepCover Secure Coprocessor
www.maximintegrated.com
Maxim Integrated
│
6
ABRIDGED DATA SHEET
