December 1990 2
Philips Semiconductors Product specification
Dual AND-OR gate 74HC58
FEATURES
• Output capability: standard
• I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 15 °C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
= C
PD
× V
CC
2
× f
i
+ ∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC
t
PHL
/ t
PLH
propagation delay C
L
= 15 pF; V
CC
= 5 V
1n to 1Y 11 ns
2n to 2Y 9 ns
C
I
input capacitance 3.5 pF
C
PD
power dissipation capacitance per
gate
notes 1 and 2 18 pF
