ISL12030IBZ-T Datasheet ISL12030IBZ-T, ISL12030IBZ | P13-P15

FN6617.2

May 5, 2011

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The 7 MSBs are the device identifier. These bits

are “1101111b” for the RTC registers and “1010111b” for the

User SRAM.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W

bit is a “1”, then a

read operation is selected. A “0” selects a write operation (see

Figure 6).

After loading the entire Slave Address Byte from the SDA bus,

the ISL12030 compares the device identifier and device select

bits with “1101111b” or “1010111b”. Upon a correct compare,

the device outputs an acknowledge on the SDA line.

Following the Slave Byte is a one byte word address. The word

address is either supplied by the master device or obtained

from an internal counter. On power-up the internal address

counter is set to address 00h, so a current address read starts

at address 00h. When required, as part of a random read, the

master must supply the 1 Word Address Byte as shown in

Figure 6.

In a random read operation, the slave byte in the “dummy write”

portion must match the slave byte in the “read” section. For a

random read of the Control/Status Registers, the slave byte

must be “1101111x” in both places.

FIGURE 3. VALID DATA CHANGES, START AND STOP CONDITIONS

FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER

FIGURE 5. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

SDA

SCL

START

DATA DATA

STOP

STABLE CHANGE

DATA

STABLE

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

81 9

START ACK

SCL FROM

MASTER

HIGH IMPEDANCE

IDENTIFICATION

BYTE

DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL12030

10011

WRITE

SIGNAL AT SDA

0000111

ADDRESS

BYTE

ISL12030

FN6617.2

May 5, 2011

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL12030 responds with an ACK. At this time, the I

interface enters a standby state.

A multiple byte operation within a page is permitted. The

Address Byte must have the start address, and the data

bytes are sent in sequence after the address byte, with the

ISL12030 sending an ACK after each byte. The page write is

terminated with a STOP condition from the master. The

pages within the ISL12030 do not support wrapping around

for page read or write operations.

Read Operation

A Read operation consists of a three byte instruction

followed by one or more Data Bytes (see Figure 7). The

master initiates the operation issuing the following

sequence: a START, the Identification byte with the RW

bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the RW

bit set to “1”. After each of the

three bytes, the ISL12030 responds with an ACK. Then the

ISL12030 transmits Data Bytes as long as the master

responds with an ACK during the SCL cycle following the

eighth bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of

the last Data Byte (see Figure 7).

The Data Bytes are from the memory location indicated by

an internal pointer. This pointers initial value is determined

by the Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the last memory location in a section or page,

the master should issue a STOP. Bytes that are read at

addresses higher than the last address in a section may be

erroneous.

FIGURE 6. SLAVE ADDRESS, WORD ADDRESS AND DATA

BYTES

SLAVE

ADDRESS BYTE

D7 D6 D5 D2D4 D3 D1 D0

A0A7 A2A4 A3 A1

DATA BYTE

A6 A5

R/W

WORD ADDRESS

SIGNALS

FROM THE

MASTER

SIGNALS FROM

THE SLAVE

SIGNAL AT

SDA

IDENTIFICATION

BYTE WITH

R/W

ADDRESS

BYTE

IDENTIFICATION

BYTE WITH

R/W

= 1

LAST READ

DATA BYTE

FIRST READ

DATA BYTE

101 1111

101

FIGURE 7. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)

ISL12030

FN6617.2

May 5, 2011

Application Section

AC Input Circuits

The AC input ideally will have a 2.5V

P-P

sine wave at the

input, so this is the target for any signal conditioning circuitry

for the 50/60Hz waveform. Note that the peak-to-peak

amplitude can range from 1V

P-P

up to V

, although it is

best to keep the max signal level just below V

. The AC

input provides DC offset so AC coupling with a series

capacitor is advised.

If the AC power supply has a transformer, the secondary

output can be used for clocking with a resistor divider and

series AC coupling capacitor. A sample circuit is shown in

Figure 8. Values for R

are chosen depending on the

peak-to-peak range on the secondary voltage in order to

match the input of the ISL12030. C

can be sized to pass

up to 300Hz or so, and in most cases, 0.47µF should be the

selected value for a ±20% tolerance device.

The AC input to the ISL12030 can be damaged if subjected

to a normal AC waveform when V

is powered down. This

can happen in circuits where there is a local LDO or power

switch for placing circuitry in standby, while the AC main is

still switched ON. Figure 8 shows a modified version of the

Figure 9 circuit, which uses an emitter follower to essentially

turn off the AC input waveform if the V

supply goes down.

Adding a Super Capacitor Backup

Since any loss of V

power will reset the SRAM memory

including control and RTC register sections, then having

some form of V

backup is a good idea. Figure 10 shows

connections for a super capacitor backup using V

for the

normal source and a signal diode for charging. Be careful

not to use a normal Schottky diode as the leakage will

greatly reduce the backup life of the super capacitor.

This form of backup should yield at least one full day of

backup time, assuming the SCL/SDA pins and their pull-ups

are pulled to ground on powerdown.

FIGURE 8. AC INPUT USING A TRANSFORMER SECONDARY

ISL12030

120VAC

50/60Hz

VIN (AC) = 1.5V

P-P

TO 5V

P-P

CIN

FIGURE 9. USING THE V

SUPPLY TO GATE THE AC INPUT

ISL12030

120VAC

50/60Hz

VIN (AC) = 1.5V

P-P

TO VDD (MAX)

CIN

VDD

ISL12030

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ISL12030IBZ-T

Mfr. #:

Buy ISL12030IBZ-T

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock REAL TIME CLK W/ EEPROM 8LD

Lifecycle:

New from this manufacturer.

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ISL12030IBZ-T

ISL12030IBZ-T

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