9
FN6617.2
May 5, 2011
Real Time Clock Registers
Addresses [00h to 07h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW, SS)
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR
(Hour) can be either 12-hour or 24-hour mode, DT (Date) is 1
to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, DW (Day of
the Week) is 0 to 6, and SS (Sub-Second) is 0 to 9. The
Sub-Second register is read-only and will clear to “0” count
each time there is a write to a register in the RTC section.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2.... The assignment of a numerical value to a specific day of
the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year and the year 2100 is not. The
ISL12030 does not correct for the leap year in the year 2100.
Status Register (SR)
Address [08h]
The Status Registers consist of the DC and AC status
registers (see Tables 2 and 3).
Status Register DC (SRDC)
The Status Register DC is located in the memory map at
address 08h. This is a volatile register that provides status of
RTC failure (RTCF), Alarm0 or Alarm1 trigger, and Daylight
Saving Time adjustment.
DAYLIGHT SAVING TIME ADJUSTMENT BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjustment Bit. It
indicates that daylight saving time adjustment has
happened. The bit will be set to “1” when the Forward DST
event has occurred. The bit will stay set until the Reverse
DST event has happened. The bit will also reset to “0” when
the DSTE bit is set to “0” (DST function disabled). The bit
can be forced to “1” with a write to the Status Register. The
default value for DSTADJ is “0”.
ALARM BITS (ALM0 AND ALM1)
These bits announce if an alarm matches the real time clock.
If there is a match, the respective bit is set to “1”. This bit can
be manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in
the SR can only set it to “0”, not “1”. An alarm bit that is set by
an alarm occurring during an SR read operation will remain
set after the read operation is complete.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (internally) when the device
powers up after having lost all power (defined as V
DD
= 0V).
The bit is set as soon as V
DD
is applied to the device. The
first valid write to the RTC section after a complete power
failure resets the RTCF bit to “0” (writing one byte is
sufficient).
Control Registers
Addresses [0Ch to 13h]
The control registers (INT, AC) contain all the bits necessary
to control the parametric functions on the ISL12030.
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM0
and ALM1 status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the SRDC
Register (with a valid STOP condition). When the ARST is
cleared to “0”, the user must manually reset the ALM0 and
ALM1 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Register section. The factory default setting of this bit is
“0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle. This bit will remain set until reset to “0” or a
complete power-down occurs (V
DD
= 0.0V).
ALARM INTERRUPT MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarms will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ
pin when the RTC is triggered
by either alarm as defined by the Alarm0 section (1Dh to
22h) or the Alarm1 section (23h to 28h). When the IM bit is
TABLE 2. STATUS REGISTER DC (SRDC)
ADDR 7 6 5 4 3 2 1 0
08h X DSTADJ ALM1 ALM0 X X X RTCF
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR 7 6 5 4 3 2 1 0
0Ch ARST WRTC IM X X X ALE1 ALE0
ISL12030
