ISL12030IBZ Datasheet ISL12030IBZ-T, ISL12030IBZ | P10-P12

FN6617.2

May 5, 2011

cleared to “0”, the alarm will operate in standard mode,

where the IRQ

pin will be set LOW until both the

ALM0/ALM1 status bits are cleared to “0”.

ALARM 1 (ALE 1)

This bit enables the Alarm1 function. When ALE1 = “1”, a

match of the RTC section with the Alarm1 section will result

is setting the ALM1 status bit to “1” and the IRQ

output LOW.

When set to “0”, the Alarm1 function is disabled.

ALARM 0 (ALE 0)

This bit enables the Alarm0 function. When ALE0 = 1, a

match of the RTC section with the Alarm1 section will result

is setting the ALM0 status bit to “1” and the IRQ

output LOW.

When set to “0”, the Alarm0 function is disabled.

AC Register (AC)

Address [13h]

This register sets the parameters for the AC input.

AC 50/60HZ INPUT SELECT (AC5060)

This bit selects either 50Hz or 60Hz powerline AC clock

input frequency. Setting this bit to “0” selects a 60Hz input

(default). Setting this bit to “1” selects a 50Hz input.

DST Control Registers (DSTCR)

Address [15h to 1Ch]

8 bytes of control registers have been assigned for the

Daylight Savings Time (DST) functions. DST beginning (set

Forward) time is controlled by the registers DstMoFd,

DstDwFd, DstDtFd, and DstHrFd. DST ending time (set

Backward or Reverse) is controlled by DstMoRv, DstDwRv,

DstDtRv and DstHrRv.

Tables 5 and 6 describe the structure and functions of the

DSTCR.

DST FORWARD REGISTERS (15H TO 18H)

DSTE is the DST Enabling Bit located in bit 7 of register 15h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.

Upon powering up for the first time, the DSTE bit defaults to

“0”.

DST forward is controlled by the following DST Registers:

DstMoFd sets the Month that DST starts. The default value

for the DST begin month is April (04h)

DstDwFd sets the Week and the Day of the Week that DST

starts. DstDwFdE sets the priority of the Day of the Week

over the Date. For DstDwFdE = 1, Day of the week is the

priority. Note that Day of the week counts from 0 to 6, like the

RTC registers. The default for the DST Forward Day of the

Week is Sunday (00h).

WkFd controls the week of the month that the DST starts.

When the day of week option is selected, the WkFd entry set

the week in the month and the DwFd selects the day of the

week. The range for WdFd is 1 to 5 and 7 with 7 being the

last week. Default is 0 (OFF).

DstDtfd controls which Date DST begins. The default value

for DST forward date is on the first date of the month (01h).

DstDtFd is only effective if DwFdE = 0.

DstHrFd controls the hour that DST begins. It includes the

MIL bit, which is in the corresponding RTC register. The RTC

hour and DstHrFd registers need to match formats (Military

or AM/PM) in order for the DST function to work. The default

value for DST hour is 2:00AM (02h). The time is advanced

from 2:00:00AM to 3:00:00AM for this setting.

DST REVERSE REGISTERS (19H TO 1CH)

DST end (reverse) is controlled by the following DST

Registers:

DstMoRv sets the Month that DST ends. The default value

for the DST end month is October (10h).

DstDwRv controls the Week and the Day of the Week that

DST should end. The DwRvE bit sets the priority of the Day of

the Week over the Date. For DwRvE = 1, Day of the week is

the priority. Note that Day of the week counts from 0 to 6, like

the RTC registers. The default for DST DwRv end is Sunday

(00h).

WkRv controls the week of the month that the DST starts.

When the day of week option is selected, the WkRv entry set

the week in the month and the DwRv selects the day of the

week. The range for WdRv is 1 to 5 and 7 with 7 being the

last week. Default is 0 (OFF)

DstDtRv controls which Date DST ends. The default value

for DST Date Reverse is on the first date of the month. The

DstDtRv is only effective if the DwRvE = 0.

DstHrRv controls the hour that DST ends. It includes the MIL

bit, which is in the corresponding RTC register. The RTC

hour and DstHrRv registers need to match formats (Military

or AM/PM) in order for the DST function to work. The default

value sets the DST end at 2:00AM. The time is set back from

2:00:00AM to 1:00:00AM for this setting.

TABLE 4. AC REGISTER

ADDR 7 6 5 4 3 2 1 0

13h AC5060 X X X X X X X

ISL12030

FN6617.2

May 5, 2011

ALARM Registers (1Dh to 28h)

The alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode.

Single Event Mode is enabled by setting either ALE0 or

ALE1 to 1, then setting bit 7 on any of the Alarm registers

(ESCA... EDWA) to “1”, and setting the IM bit to “0”. This

mode permits a one-time match between the Alarm registers

and the RTC registers. Once this match occurs, the ALM bit

is set to “1” and the IRQ

output will be pulled LOW and will

remain LOW until the ALM bit is reset. This can be done

manually or by using the auto-reset feature. Since the IRQ

output is shared by both alarms, they both need to be reset

in order for the IRQ

output to go HIGH.

Interrupt Mode is enabled by setting either ALE0 or ALE1 to

1, then setting bit 7 on any of the Alarm registers (ESCA...

EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit

to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ

output will now be pulsed each time an alarm occurs (either

AL0 or AL1). This means that once the interrupt mode alarm

is set, it will continue to alarm until it is reset.

To clear a single event alarm, the corresponding ALM0 or

ALM1 bit in the SRDC register must be set to “0” with a write.

Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the

ALM0 and ALM1 bits will automatically be cleared when the

status register is read.

The IRQ

output will be set by an alarm match for either

ALM0 or ALM1.

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1

• Alarm set with single interrupt (IM = ”0”)

• A single alarm will occur on January 1 at 11:30am

• Set Alarm registers as follows:

After these registers are set, an alarm will be generated when

the RTC advances to exactly 11:30 a.m. on January 1 (after

seconds changes from 59 to 00) by setting the ALM0 bit in the

status register to “1” and also bringing the IRQ

output LOW.

TABLE 5. DST FORWARD REGISTERS

ADDRESS FUNCTION 7 6 5 4 3 2 1 0

15h Month Forward DSTE 0 0 MoFd20 MoFd13 MoFd12 MoFd11 MoFd10

16h Day Forward 0 DwFdE WkFd12 WkFd11 WkFd10 DwFd12 DwFd11 DwFd10

17h Date Forward 0 0 DtFd21 DtFd20 DtFd13 DtFd12 DtFd11 DtFd10

18h Hour Forward HrFdMIL 0 HrFd21 HrFd20 HrFd13 HrFd12 HrFd11 HrFd10

TABLE 6. DST REVERSE REGISTERS

ADDRESS NAME 7 6 5 4 3 2 1 0

19h Month Reverse 0 0 0 MoRv20 MoRv13 MoRv12 MoRv11 MoRv10

1Ah Day Reverse 0 DwRvE WkRv12 WkRv11 WkRv10 DwRv12 DwRv11 DwRv10

1Bh Date Reverse 0 0 DtRv21 DtRv20 DtRv13 DtRv12 DtRv11 DtRv10

1Ch Hour Reverse HrRvMIL 0 HrRv21 HrRv20 HrRv13 HrRv12 HrRv11 HrRv10

ALARM

BIT

DESCRIPTION76543210HEX

SCA0 00000000 00hSeconds disabled

MNA0 10110000 B0hMinutes set to 30,

enabled

HRA0 10010001 91hHours set to 11,

enabled

DTA0 10000001 81hDate set to 1,

enabled

MOA0 10000001 81hMonth set to 1,

enabled

DWA0 00000000 00hDay of week

disabled

ISL12030

FN6617.2

May 5, 2011

Example 2

• Pulsed interrupt once per minute (IM = ”1”)

• Interrupts at one minute intervals when the seconds

• Set Alarm registers as follows:

Once the registers are set, the following waveform will be

seen at IRQ

as shown in Figure 2:

Note that the status register ALM0 bit will be set each time

the alarm is triggered, but does not need to be read or

cleared.

User Memory Registers (accessed by

using Slave Address 1010111x)

Addresses [00h to 7Fh]

These registers are 128 bytes of user SRAM. Writes to this

section do not need to be proceeded by setting the WRTC

bit. Note that this memory, like the status and control

registers, is volatile and will be lost or corrupted when V

drops below 1.8V.

C Serial Interface

The ISL12030 supports a bi-directional bus oriented

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is the master

and the device being controlled is the slave. The master

always initiates data transfers and provides the clock for

both transmit and receive operations. Therefore, the

ISL12030 operates as a slave device in all applications.

All communication over the I

C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (see

Figure 3). On power-up of the ISL12030, the SDA pin is in

the input mode.

All I

C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL12030 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (see

Figure 3). A START condition is ignored during the power-up

sequence.

All I

C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (see Figure 3). A STOP condition at the end of

a read operation or at the end of a write operation to memory

only places the device in its standby mode.

An acknowledge (ACK) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (See Figure 4).

The ISL12030 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL12030 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

ALARM

BIT

DESCRIPTION76543210HEX

SCA0 10110000B0hSeconds set to 30,

enabled

MNA0 0000000000hMinutes disabled

HRA0 0000000000hHours disabled

DTA0 0000000000hDate disabled

MOA0 0000000000hMonth disabled

DWA0 0000000000hDay of week disabled

60s

RTC AND ALARM REGISTERS ARE BOTH “30s”

FIGURE 2. IRQ WAVEFORM

ISL12030

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ISL12030IBZ

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