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CAT1641YI-28-GT3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CAT1640, CAT1641
http://onsemi.com
10
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W
bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8−bit
address bytes that are to be written into the address pointers
of the device. After receiving another acknowledge from the
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1640/41
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
Figure 5. Start/Stop Timing
START BIT
A
SD
STOP BIT
SCL
Figure 6. Acknowledge Timing
ACKNOWLEDGE
1
RTSTA
SCL FROM
MASTER
8
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
9
Figure 7. Slave Address Bits
1
Default Configuration
0 1 0 A2 A1 A0 R/W
Page Write
The CAT1640/41 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to
additional 63 bytes. After each byte has been transmitted, the
CAT1640/41 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1640/41 in a single write cycle.
CAT1640, CAT1641
http://onsemi.com
11
Figure 8. Byte Write Timing
* = Don’t Care Bit
A
15
–A
8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A
7
–A
0
BYTE ADDRESS
A
C
K
*
**
Figure 9. Page Write Timing
* = Don’t Care Bit
A
15
–A
8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A
7
–A
0
BYTE ADDRESS
DATA n+63DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
*
**
BUS
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1640/41 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the device is still busy with the write operation,
no ACK will be returned. If a write operation has completed,
an ACK will be returned and the host can then proceed with
the next read or write operation.
Read Operations
The READ operation for the CAT1640/41 is initiated in
the same manner as the write operation with one exception,
that R/W
bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Figure 10. Immediate Address Read Timing
SCL
SDA8TH BIT
STOPNO ACKDATA OUT
8
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
9
CAT1640, CAT1641
http://onsemi.com
12
Immediate/Current Address Read
The CAT1640 and CAT1641 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1640 and CAT1641 receives its
slave address information (with the R/W
bit set to one), it
issues an acknowledge, then transmits the 8−bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1640 and CAT1641 acknowledges, the Master
device sends the START condition and the slave address
again, this time with the R/W
bit set to one. The CAT1640
and CAT1641 then responds with its acknowledge and sends
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
initial 8−bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1640 and CAT1641 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1640 and
CAT1641 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1640 and
CAT1641 address bits so that the entire memory array can
be read during one operation.
Figure 11. Selective Read Timing
* = Don’t Care Bit
A
15
–A
8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A
7
–A
0
BYTE ADDRESS SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
DATA
P
*
*
*
S
T
A
R
T
S
T
O
P
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+xDATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CAT1641YI-28-GT3

Mfr. #:
Buy CAT1641YI-28-GT3
Manufacturer:
ON Semiconductor
Description:
Supervisory Circuits CPU SUP W/64K EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
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