7
Det_Ref
Det_Out
Det_Ref - Det_Out
Application and Usage
Biasing and Operation
The recommended quiescent DC bias condition for
optimum efficiency, performance, and reliability is Vd = 5
volts with Vg set for Id = 650mA. The drain bias voltage
range is 3 to 5V and must be applied to both sides of the
IC. A single DC gate supply connected to Vg, from either
side of the IC, will bias all gain stages. Muting can be
accomplished by setting Vg to the pinch-off voltage Vp
(~ -2V).
Care must be taken to not exceed the absolute
maximum pinch-off voltage as this will cause the ESD protec-
tion diodes to turn on thus causing a substantial increase in
gate current.
An optional output power detector network is also
provided. The differential voltage between the Det-Ref
and Det-Out pads can be correlated with the RF power
emerging from the RF output port. The detected voltage
is given by :
V = (V
ref
– V
det
) – V
ofs
where V
ref
is the voltage at the DET_R port, V
det
is a volt-
age at the DET_O port, and V
ofs
is the zero-input-power
offset voltage. There are three methods to calculate V
ofs
:
1) V
ofs
can be measured before each detector measure-
ment (by removing or switching off the power source
and measuring V
ref
– V
det
). This method gives an error
due to temperature drift of less than 0.01dB/50°C.
2) V
ofs
can be measured at a single reference temperature.
The drift error will be less than 0.25dB.
3) V
ofs
can either be characterized over temperature and
stored in a lookup table, or it can be measured at two
temperatures and a linear fit used to calculate V
ofs
at
any temperature. This method gives an error close to
method #1.
Figure 11 illustrates the typical performance for detector
sensitivity vs. Pin. With <0dBm RF input, the diode does
not turn on; thus, [Det_R – Det_Out = 0]. As RF power
increases the diode turns on harder; thus, [Det_R –
Det_Out] increases.
The RF ports are AC coupled at the RF input to the first
stage and the RF output of the final stage. No ground
wires are needed since ground connections are made
with plated through-holes to the backside of the device.
Assembly Techniques
The chip should be attached directly to the ground plane
using electrically conductive epoxy
[1]
. For conductive
epoxy, the amount should be just enough to provide a thin
fillet around the bottom perimeter of the die. The ground
plane should be free of any residue that may jeopardize
electrical or mechanical attachment. Caution should be
taken to not exceed the Absolute Maximum Rating for
assembly temperature and time.
Thermo-sonic wedge bonding is the preferred method
for wire attachment to the bond pads. The RF connec-
tions should be kept as short as possible to minimize
inductance. 0.7mil gold wire is recommended. The recom-
mended wire bonding stage temperature is 150±2°C.
The chip is 100μm thick and should be handled with care.
This MMIC has exposed air bridges on the top surface.
Handle at the edges or with a custom collet (do not pick
up die with vacuum on die center).
This MMIC is also static sensitive and ESD handling pre-
cautions should be taken.
For more detailed information, see Avago Application Note
54 “GaAs MMIC ESD, Die Attach and Bonding Guide lines.”
Notes:
1. Sumitomo 1295SA silver epoxy is recommended.
2. Eutectic attach is not recommended and may jeopardize reliability of
the device.
Figure 11. Detector vs. Pin
