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ISL6520IBZ-T

P1-P3P4-P6P7-P9P10-P11
4
FN9009.6
April 3, 2007
Functional Pin Description
VCC
This is the main bias supply for the ISL6520, as well as the
lower MOSFET’s gate. Connect a well-decoupled 5V supply
to this pin.
FB
This pin is the inverting input of the internal error amplifier. Use
this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET source. This pin is
used to monitor the voltage drop across the upper MOSFET
for over-current protection. This pin is also monitored by the
continuously adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET
This is a multiplexed pin. During a short period of time following
power-on reset (POR), this pin is used to determine the over-
current threshold of the converter. Connect a resistor (R
OCSET
)
from this pin to the drain of the upper MOSFET (V
CC
).
R
OCSET
, an internal 20A current source (I
OCSET
), and the
upper MOSFET on-resistance (r
DS(ON)
) set the converter over-
current (OC) trip point according to the following equation:
Internal circuitry of the ISL6520 will not recognize a voltage
drop across R
OCSET
larger than 0.5V. Any voltage drop
across R
OCSET
that is greater than 0.5V will set the
overcurrent trip point to:
An over-current trip cycles the soft-start function.
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error amplifier.
Use this pin, in combination with the FB pin, to compensate the
voltage-control feedback loop of the converter.
Pulling OCSET to a level below 0.8V will disable the
controller. Disabling the ISL6520 causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
Do not insert any circuitry between this pin and the gate of the
lower MOSFET, as it may interfere with the internal adaptive
shoot-through protection circuitry and render it ineffective.
Functional Description
Initialization
The ISL6520 automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Over-Current Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
Over Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r
DS(ON)
, to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor
(R
OCSET
) programs the over-current trip level (see See
“Typical Application” on page 2.).
Immediately following POR, the ISL6520 initiates the Over-
Current Protection sampling and hold operation. First, the
internal error amplifier is disabled. This allows an internal
20A current sink to develop a voltage across R
OCSET
. The
ISL6520 then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Over-Current Set Point.
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Over-Current Set
Point, the over-current function initiates a soft-start sequence.
Figure 1 shows the inductor current after a fault is introduced
while running at 15A. The continuous fault causes the
ISL6520 to go into a hiccup mode with a typical period of
25ms. The inductor current increases to 18A during the Soft
I
PEAK
I
OCSET
xR
OCSET
r
DS ON
-------------------------------------------------=
(EQ. 1)
I
PEAK
0.5V
r
DS ON
----------------------=
(EQ. 2)
ISL6520
5
FN9009.6
April 3, 2007
Start interval and causes an over-current trip. The converter
dissipates very little power with this method. The measured
input power for the conditions of Figure 1 is only 1.5W.
The over-current function will trip at a peak inductor current
(I
PEAK)
determined by:
where I
OCSET
is the internal OCSET current source (20A
typical). The OC trip point varies mainly due to the
MOSFET’s r
DS(ON)
variations. To avoid over-current tripping
in the normal operating load range, find the R
OCSET
resistor
from the equation above with:
1. The maximum r
DS(ON)
at the highest junction
temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for
,
whereI is the output inductor ripple current.
For an equation for the ripple current, see“Output Inductor
Selection” on page 7.
Soft-Start
The POR function initiates the soft-start sequence after the
overcurrent set point has been sampled. Soft-start clamps the
error amplifier output (COMP pin) and reference input (non-
inverting terminal of the error amp) to the internally generated
Soft-Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the oversurrent setpoint by disabling the error
amplifier and drawing 20A through R
OCSET
. Once the over-
current level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter’s output voltage during soft start.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). When the
internally generated Soft-Start voltage exceeds the feedback
(FB pin) voltage, the output voltage is in regulation. This
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors C
IN
and C
O
may each
represent numerous physical capacitors. Locate the ISL6520
within 3 inches of the MOSFETs, Q
1
and Q
2
. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520 must be sized to handle up to 1A peak current.
FIGURE 1. OVERCURRENT OPERATION
TIME (5ms/DIV.)
OUTPUT
INDUCTOR
5A/DIV.
CURRENT
I
PEAK
I
OCSET
x R
OCSET
r
DS ON
-----------------------------------------------------=
(EQ. 3)
I
PEAK
I
OUT MAX
I
2
----------
+>
FIGURE 2. START UP SEQUENCE
V
OUT
500mV/DIV.
COMP/OCSET
1V/DIV.
TIME (2ms/DIV.)
L
O
C
O
LGATE
UGATE
PHASE
Q
1
Q
2
V
IN
V
OUT
RETURN
ISL6520
C
IN
LOAD
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
ISL6520
6
FN9009.6
April 3, 2007
Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, R
OSCET
close
to the COMP/OCSET pin because the internal current source is
only 20A. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical to
the BOOT and PHASE pins. All components used for feedback
compensation should be located as close to the IC a practical.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
IN
at
the PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6520) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage V
OSC
.
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+5V
ISL6520
COMP/OCSET
GND
VCC
BOOT
D
1
L
O
C
O
V
OUT
LOAD
Q
1
Q
2
PHASE
+V
IN
C
BOOT
C
VCC
R
OCSET
+5V
F
LC
1
2 x L
O
x C
O
-------------------------------------------= F
ESR
1
2 x ESR x C
O
--------------------------------------------=
(EQ. 4)
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
2
C
1
COMP
V
OUT
FB
Z
FB
ISL6520
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
F
Z1
1
2 x R
2
x C
1
------------------------------------=
F
Z2
1
2 x R
1
R
3
+ x C
3
-------------------------------------------------------=
F
P1
1
2 x R
2
x
C
1
x C
2
C
1
C
2
+
----------------------



---------------------------------------------------------=
F
P2
1
2 x R
3
x C
3
------------------------------------=
(EQ. 5)
ISL6520
P1-P3P4-P6P7-P9P10-P11

ISL6520IBZ-T

Mfr. #:
Buy ISL6520IBZ-T
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 8LD C4AM SINGLE 5V PWM CONT STD OUT
Lifecycle:
New from this manufacturer.
Delivery:
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