ISL6520IBZ-T

7
FN9009.6
April 3, 2007
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6520 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk
capacitors to supply the current needed each time Q
1
turns
on. Place the small ceramic capacitors physically close to
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
F
LC
F
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
20LOG
(V
IN
/DV
OSC
)
MODULATOR
GAIN
(R
2
/R
1
)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
I =
V
IN
- V
OUT
Fs x L
V
OUT
V
IN
V
OUT
= I x ESR
x
(EQ. 6)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 7)
ISL6520
8
FN9009.6
April 3, 2007
the MOSFETs and between the drain of Q
1
and the source
of Q
2
.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
MOSFET Selection/Considerations
The ISL6520 requires two N-Channel power MOSFETs.
These should be selected based upon r
DS(ON)
, gate
supply requirements, and thermal management
requirements.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only
the upper MOSFET has switching losses, since the lower
MOSFETs body diode or an external Schottky rectifier
across the lower MOSFET clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of
the lower MOSFET’s body diode. The gate-charge losses
are dissipated by the ISL6520 and don't heat the
MOSFETs. However, large gate-charge increases the
switching interval, t
SW
which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Given the reduced available gate bias voltage (5V),
logic-level or sub-logic-level transistors should be used for
both N-MOSFETs. Caution should be exercised with
devices exhibiting very low V
GS(ON)
characteristics. The
shoot-through protection present aboard the ISL6520 may
be circumvented by these MOSFETs if they have large
parasitic impedences and/or capacitances that would
inhibit the gate of the MOSFET from being discharged
below its threshold level before the complementary
MOSFET is turned on.
Figure 7 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from V
CC
. The boot capacitor,
C
BOOT
, develops a floating supply voltage referenced to
the PHASE pin. The supply is refreshed to a voltage of V
CC
less the boot diode drop (V
D
) each time the lower
MOSFET, Q
2
, turns on.
P
UPPER
= Io
2
x r
DS(ON)
x D +
1
2
Io x V
IN
x t
SW
x F
S
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the switching interval, and
F
S
is the switching frequency.
(EQ. 8)
+5V
ISL6520
GND
LGATE
UGATE
PHASE
BOOT
VCC
+5V
NOTE:
NOTE:
V
G-S
V
CC
C
BOOT
D
BOOT
Q1
Q2
+
-
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
V
G-S
V
CC
-V
D
+ V
D
-
ISL6520
9
FN9009.6
April 3, 2007
ISL6520 DC/DC Converter Application Circuit
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete Bill-
of-Materials and circuit board description, can be found in
Application Note AN9932.
Component Selection Notes:
C
IN
- Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
C
OUT
- Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent.
D1 - 30mA Schottky Diode, MA732 or Equivalent
L
1
- 3.1H Inductor, Panasonic P/N ETQ-P6F2ROLFA or Equivalent.
Q
1
, Q
2
- Intersil MOSFET; HUF76143.
FIGURE 8. 5V to 3.3V 15A DC/DC CONVERTER
+5V
V
OUT
FB
COMP/OCSET
UGATE
PHASE
BOOT
VCC
GND
LGATE
+
5
7
6
3
2
1
8
4
ISL6520
+
3.16k
L
1
C
OUT
D
1
0.1F
C
IN
2 x 1F
Q
1
Q
2
U
1
0.1F
MONITOR
AND
PROTECTION
REF
OSC
+
-
-
+
3 x 330F
2 x 330F
0.1F
1.00k
10.0k
470pF
8200pF
6.19k
60.4 18000pF
ISL6520

ISL6520IBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 8LD C4AM SINGLE 5V PWM CONT STD OUT
Lifecycle:
New from this manufacturer.
Delivery:
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