IDT5V19EE403
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR 28
IDT5V19EE403 REV M 092412
Revision History
Rev. Date Originator Description of Change
A 4/27/09 R.Willner Advance Information.
B 5/04/09 R.Willner Identified VDDX (crystal oscillator power) and AVDD (analog power) on device.
C 6/04/09 R.Willner Add default configurations, pull-down resistor values on input pins.
Released Datasheet from Advanced Information.
D 06/10/09 R.Willner Updates: crystal load specs; “Output Duty Cycle” specs; addresses 0x07, 0x02 and 0xBF
in “Programming Registers” table.
E 10/05/09 R.Willner Change IP3[3:0] to IP3[4:0]; updated “Programming Registers Table”.
F 02/23/10 R.Willner Updated Recommended Operating Conditions to include separate 3.3V Vddx and AVdd
parameters
G 01/19/11 R.Willner Corrected notes for top-side marking.
H 04/22/11 R.Willner Added Landing Pattern diagram.
J 04/18/12 R. Willner 1. Change description for SDAT and SCLK pins.
2. Add new footnotes to pin descriptions table
3. Added section "Crystal Clock Selection"
4. Added logic diagram and Truth table for "SD/OE Pin Function" section.
5. Corrected register readback values for 0x52~0x54 and 0x7C~0x7F.
6. Update to QFN package drawing - exposed thermal pad callout.
K 06/04/12 A. Tsui 1. Updated SD-OE pin description; from (Default is active HIGH) to (Default is active
LOW)
2. Updated “OUTn” column in Truth Table with “High-Z” specs and added footnote 2,
“High-Z regardless of OEM bits”.
3. Updated “SD-OE Pin Function” section to reflect that SP is “0”changed from active
HIGH to active LOW, and SP is “1” changed from active LOW to active HIGH.
L 06/18/12 R.Willner Added Min/Max spread values to "Spread Spectrum Generation Specifications" table;
fMOD - Max. 120kHz; Down Spread - Min. -0.5%, Max. -4.0%; Center Spread - Min.
±0.25%, Max. ±2.0%
M 09/24/12 R.Willner Slew Rate (t4) Output Load test conditions were changed from 15pF to 5pF.
