74LVC16373APVG

INDUSTRIAL TEMPERATURE RANGE
4
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol Parameter Test Conditions Typical Unit
CPD Power Dissipation Capacitance per Latch Outputs enabled CL = 0pF, f = 10Mhz 39 pF
CPD Power Dissipation Capacitance per Latch Outputs disabled 6
SWITCHING CHARACTERISTICS
(1)
VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Unit
tPLH Propagation Delay 4.9 1.6 4.2 ns
tPHL xDx to xQx
tPLH Propagation Delay 5.3 2.1 4.6 ns
tPHL xLE to xQx
tPZH Output Enable Time 5.7 1.3 4.7 ns
tPZL xOE to xQx
t
PHZ Output Disable Time 6.3 2.5 5.9 ns
tPLZ xOE to xQx
tSU Set-up Time, data before LE HIGH or LOW 1.7 1.7 ns
tH Hold Time, data after LE HIGH or LOW 1.2 1.2 ns
tW Pulse Width LE HIGH 3.3 3.3 ns
tSK(o) Output Skew
(2)
—— 500 ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
5
Open
VLOAD
GND
VCC
Pulse
Generator
D.U.T.
500
500
CL
RT
VIN
VOUT
(1, 2)
LVC Link
INPUT
VIH
0V
V
OH
VOL
tPLH1
tSK (x)
OUTPUT 1
OUTPUT 2
t
PHL1
tSK (x)
tPLH2
tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
VOL
tPLH
tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
LVC Link
DATA
INPUT
0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
tH
tSU
tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
LVC Link
CONTROL
INPUT
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
tPHZ
0V
V
OL+VLZ
VOH
VT
VT
tPZL
VLOAD/2
VLOAD/2
VIH
VT
VOL
VOH-VHZ
LVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC
(1)
= 3.3V±0.3V VCC
(1)
= 2.7V VCC
(2)
= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT 1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
C
L 50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low V
LOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
6
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
ORDERING INFORMATION
XX
LVC
XXXX
XX
Package
Device Type
Temp. Range
PVG
PAG
16
74
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
16-Bit Transparent D-Type Latch with 3-State Outputs
-40°C to +85°C
XXX
Family
Bus-Hold
373A
No Bus-hold
Double-Density, ±24mA
Blank
X
Blank
8
Tube or Tray
Tape and Reel
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
DATASHEET DOCUMENT HISTORY
07/28/2015 Pg. 6 Updated the ordering information by removing non RoHS parts and adding Tape and Reel information.

74LVC16373APVG

Mfr. #:
Manufacturer:
IDT
Description:
Latches 16-bit Transparent D-Type Latch
Lifecycle:
New from this manufacturer.
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