Rev. 1.3 4/16 Copyright © 2016 by Silicon Laboratories Si53154
Si53154
PCI-E
XPRESS
G
EN
1, G
EN
2, G
EN
3,
AND
G
EN
4 Q
UAD
F
ANOUT
B
UFFER
Features
Applications
Description
The Si53154 is a spread spectrum tolerant PCIe clock buffer that can source
four PCIe clocks simultaneously. The device has four hardware output enable
control inputs for enabling the respective differential outputs on the fly. The
device also features output enable control through I
2
C communication. I
2
C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at www.silabs.com/pcie-learningcenter.
Functional Block Diagram
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock
compliant
Supports Serial ATA (SATA) at
100 MHz
100–210 MHz operation
Low power, push pull, differential
output buffers
Internal termination for maximum
integration
Dedicated output enable pin for
each output
Four PCI-Express buffered clock
outputs
Clock input spread tolerable
Supports LVDS outputs
I
2
C support with readback
capabilities
Extended temperature:
–40 to 85 °C
3.3 V power supply
24-pin QFN package
Network attached storage
Multi-function printers
Wireless access point
Routers
Control RAM
Control & Memory
DIFFIN
DIFFIN
SCLK
SDATA
OE [3:0]
DIFF0
DIFF1
DIFF2
DIFF3
Patents pending
Ordering Information:
See page 17.
Pin Assignments
VDD
OE1*
VDD
VSS
VDD
OE2*
VSS
DIFFIN
DIFFIN
1
2
3
4
5
6
24 23 22 21 20 19
7 8 9 10 11 12
18
17
16
15
14
13
OE0*
DIFF0
DIFF0
DIFF1
DIFF1
VDD
VDD
SDATA
SCLK
OE3*
VDD
DIFF3
DIFF3
DIFF2
DIFF2
*Note: Internal 100 kohm pull-up.
25
GND
