Si53154
6 Rev. 1.3
Additive PCIe Gen 4 Phase
Jitter
RMS
GEN4
PCIe Gen 4 — — 0.10 ps
Additive Cycle to Cycle Jitter T
CCJ
Measured at 0 V differential — 20 50 ps
Long-term Accuracy L
ACC
Measured at 0 V differential — — 100 ppm
Rising/Falling Slew rate T
R
/T
F
Measured differentially from
±150 mV
2.5 — 8 V/ns
Crossing Point Voltage at
0.7 V Swing
V
OX
300 — 550 mV
Enable/Disable and Setup
Clock Stabilization from
Power-Up
T
STABLE
Measured from the point when both
V
DD
and clock input are valid
—— 5ms
Stopclock Set-up Time T
SS
10.0 — — ns
Table 3. Absolute Maximum Conditions
Parameter Symbol Condition Min Typ Max Unit
Main Supply Voltage V
DD_3.3V
Functional — — 4.6 V
Input Voltage V
IN
Relative to V
SS
–0.5 — 4.6 V
DC
Temperature, Storage T
S
Non-functional –65 — 150 °C
Industrial Temperature, Operating
Ambient
T
A
Functional –40 — 85 °C
Commercial Temperature, Operating
Ambient
T
A
Functional 0 — 85 °C
Temperature, Junction T
J
Functional — — 150 °C
Dissipation, Junction to Case Ø
JC
JEDEC (JESD 51) — — 25 °C/W
Dissipation, Junction to Ambient Ø
JA
JEDEC (JESD 51) — — 37 °C/W
ESD Protection (Human Body Model) ESD
HBM
JEDEC (JESD 22 - A114) 2000 — – V
Flammability Rating UL-94 UL (Class) V–0
Note: Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply
sequencing is not required.
Table 2. AC Electrical Specifications (Continued)
Parameter Symbol Condition Min Typ Max Unit
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
