RXM-900-HP3-PPO Datasheet RXM-900-HP3-SPS, RXM-900-HP3-PPO | P4-P6

THEORY OF OPERATION

The HP3 is a high-performance multi-channel, dual-conversion superhet

receiver capable of recovering both analog (FM) and digital (FSK) information

from a matching HP Series transmitter. FM / FSK modulation offers significant

advantages over AM or OOK modulation methods, including increased noise

immunity and the receiver’s ability to capture in the presence of multiple signals.

This is especially helpful in crowded bands, like that in which the HP3 operates.

The single-ended RF port is matched to 50-ohms to support commonly available

antennas, such as those manufactured by Linx. The RF signal coming in from

the antenna is filtered by a Surface Acoustic Wave (SAW) filter to attenuate

unwanted RF energy. A SAW filter provides significantly higher performance

than other filter types, such as an LC bandpass filter.

Once filtered, the signal is amplified by a Low Noise Amplifier (LNA) to increase

the receiver sensitivity and lower the overall noise figure of the receiver. After the

LNA, the signal is mixed with a synthesized local oscillator operating 34.7MHz

below the incoming transmission frequency to produce the first Intermediate

Frequency (IF).

The second conversion and FM demodulation is achieved by a high-

performance IF strip that mixes the 34.7MHz first conversion frequency with

24.0MHz from a precision crystal oscillator. The resulting second IF of 10.7MHz

is then highly amplified in preparation for demodulation.

A quadrature demodulator is used to recover the baseband signal from the

carrier. The demodulated waveform is filtered, after which it closely resembles

the original signal. The signal is routed to the analog output pin and the data

slicer stage, which provides squared digital output via the data output pin. A key

feature of the HP3 is the transparency of its digital output, which does not impose

balancing or duty-cycle requirements within a range of 100bps to 56kbps.

An on-board microcontroller manages receiver functions and greatly simplifies

user interface. The microcontroller reads the channel selection lines and

programs the on-board synthesizer. This frees the designer from complex

programming requirements and allows for manual or software channel selection.

The microcontroller also monitors incoming signal strength and squelches the

data output when the signal is not strong enough for accurate data detection.

Page 7Page 6

Channel

Select

SAW BPF

VCO

PLL

{

4MHz

Int. Osc.

MODE

CS0

CS1

CS2

LNA

34.7M

BPF

10.7MHz

BPF

24MHz

Crystal

Amp

10.7M

BPF

10.7M

Discriminator

Quad

RSSI

Digital

Data

Analog

Data

Limiter

Figure 9: HP3 Series Receiver Block Diagram

POWER-UP SEQUENCE

As previously mentioned, the HP3 is controlled

by an on-board microprocessor. When power

is applied, the microprocessor executes the

receiver start-up sequence, after which the

receiver is ready to receive valid data.

The adjacent figure shows the start-up

sequence. This sequence is executed when

power is applied to the V

line or when the

PDN line is taken high.

On power-up, the microprocessor reads the

external channel selection lines and sets the

frequency synthesizer to the appropriate

channel. Once the frequency synthesizer has

stabilized, the receiver is ready to accept data.

POWER SUPPLY

The HP3 incorporates a precision, low-dropout

regulator on-board, which allows operation over an

input voltage range of 2.8 to 13 volts DC. Despite this

regulator, it is still important to provide a supply that

is free of noise. Power supply noise can significantly

affect the receiver sensitivity; therefore, providing a

clean power supply for the module should be a high

priority during design.

A 10Ω resistor in series with the supply followed by a

10µF tantalum capacitor from V

to ground will help in cases where the quality

of supply power is poor. This filter should be placed close to the module’s supply

lines. These values may need to be adjusted depending on the noise present on

the supply line.

USING THE PDN PIN

The Power Down (PDN) line can be used to power down the receiver without the

need for an external switch. This line has an internal pull-up, so when it is held

high or simply left floating, the module will be active.

When the PDN line is pulled to ground, the receiver will enter into a low-current

(<10µA) power-down mode. During this time the receiver is off and cannot

perform any function. It may be useful to note that the startup time coming out

of power-down will be slightly less than when applying V

The PDN line allows easy control of the receiver state from external

components, like a microcontroller. By periodically activating the receiver,

checking for data, then powering down, the receiver’s average current

consumption can be greatly reduced, saving power in battery-operated

applications.

POWER ON

Squelch Data

Output Pin

Determine Mode

Program Freq. Synth

To Default CH. 50

Read Channel

Selection Inputs

Crystal Oscillator

Begins to Operate

Program Frequency

Synthesizer

Ready for

Serial Data Input

Crystal Oscillator

Begins to Work

Determine Squelch

State Data Output Pin

Cycle Here Until More

Data Input

or Mode Change

Determine Squelch

State Data Output Pin

Cycle Here Until

Channel

or Mode Change

Serial ModeParallel Mode

Figure 10: Start-Up Sequence

10Ω

10μF

Vcc IN

Vcc TO

MODULE

Figure 11: Supply Filter

Page 9Page 8

THE DATA OUTPUT

The DATA line outputs recovered digital data. It is an open collector output with

an internal 4.7kΩ pull-up. When an RF transmission is not present, or when the

received signal strength is too low to ensure proper demodulation, the data

output is squelched continuous high. This feature supports direct operation with

UARTs, which require their input to be continuously high. An HP3 transmitter and

receiver can be directly connected between two UARTs without the need for

buffering or logical inversion. It should be noted that the squelch level is set just

over the receiver’s internal noise threshold. Any external RF activity above that

threshold will “break squelch” and produce hashing on the line. While the DATA

line will be reliably squelched in low-noise environments, the designer should

always plan for the potential of hashing.

AUDIO OUTPUT

The HP3 Series is optimized for the transmission of serial data; however, it can

also be used very effectively to send a variety of analog signals, including audio.

The ability of the HP3 to send combinations of audio and data opens new areas

of opportunity for creative design.

The analog output of the AUDIO line is valid from 50 Hz to 28 kHz, providing an

AC signal of about 1V peak-to-peak. This is a high impedance output and not

suitable for directly driving low-impedance loads, such as a speaker. In

applications where a low impedance load is to be driven, a buffer circuit should

always be used. For example, in the case of a speaker, a simple op-amp circuit

such as the one shown below can be used to act as an impedance converter.

The transmitter’s modulation voltage is critical, since it determines the carrier

deviation and distortion. The transmitter input level should be adjusted to

achieve the optimum results for your application in your circuit. Please refer to

the transmitter data guide for full details.

When used for audio, the analog output of the receiver should be filtered and

buffered to obtain maximum sound quality. For voice, a 3-4kHz low-pass filter is

often employed. For broader-range sources, such as music, a 12-17kHz cutoff

may be more appropriate. In applications that require high-quality audio, a

compandor may be used to further improve SNR. The HP3 is capable of

providing audio quality comparable to a radio or intercom. For applications where

true high fidelity audio is required, the HP3 will probably not be the best choice,

and a device optimized for audio should be utilized.

HP Analog Out

10k

–

LM386

0.05uF

1uF

250uF

10 ohm

VCC

Figure 12: Audio Buffer Amplifier

TIMING CONSIDERATIONS

There are four major timing considerations to be aware of when designing with

the HP3 Series receiver. These are shown in the table below.

T1 is the maximum amount of time that can elapse without a data transition. Data

must always be considered in both the analog and the digital domain. Because

the data stream is asynchronous and no particular format is imposed, it is

possible for the data to meet the receiver’s data rate requirement yet violate the

analog frequency requirements. For example, if a 255 (0FF hex) were sent

continuously, the receiver would view the data as a DC level. It would hold that

level until a transition was required to meet the minimum frequency specification.

If no transition occurred, data integrity could not be guaranteed. While no

particular structure or balancing requirement is imposed, the designer must

ensure that both analog and digital signals meet the transition specification.

T2 is the worst-case time needed for a powered-up module to switch between

channels after a valid channel selection. This time does not include external

overhead for loading a desired channel in the serial channel-selection mode.

T3 is the time to receiver readiness from the PDN line going high. Receiver

readiness is determined by valid data on the DATA line. This assumes an

incoming data stream and the presence of stable supply on V

T4 is the time to receiver readiness from the application of V

. Receiver

readiness is determined by valid data on the DATA line. This assumes an

incoming data stream and the PDN line is high or open.

RECEIVING DATA

Once an RF link has been established, the challenge becomes how to effectively

transfer data across it. While a properly designed RF link provides reliable data

transfer under most conditions, there are still distinct differences from a wired link

that must be addressed. Since the modules do not incorporate internal encoding

or decoding, the user has tremendous flexibility in how data is handled.

It is important to separate the types of transmissions that are technically possible

from those that are legally allowed in the country of operation. Application Notes

AN-00126, AN-00140 and Part 15, Section 249 of the FCC rules should be

reviewed for details on acceptable transmission content in the U.S.

If you want to transfer simple control or status signals (such as button presses)

and your product does not have a microprocessor or you wish to avoid protocol

development, consider using an encoder / decoder IC set. These chips are

available from several manufacturers, including Linx. They take care of all

encoding and decoding functions and provide a number of data lines to which

switches can be directly connected. Address bits are usually provided for

security and to allow the addressing of multiple receivers independently. These

ICs are an excellent way to bring basic remote control products to market quickly

and inexpensively. It is also a simple task to interface with inexpensive

microprocessors or one of many IR, remote control, DTMF, or modem ICs.

Parameter Description Max.

T1 Time between DATA output transitions 20.0mS

T2 Channel change time (time to valid data) 1.5mS

T3 Receiver turn-on time via PDN 3.0mS

Receiver turn-on time via V

7.0mS

Page 11Page 10

*See NOTE on previous page.

SERIAL CHANNEL SELECTION TABLE

CHANNEL TX FREQUENCY RX LO CHANNEL TX FREQUENCY RX LO

0 902.62 867.92 51 915.37 880.67

1 902.87 868.17 52 915.62 880.92

2 903.12 868.42 53 915.87 881.17

3 903.37 868.67 54 916.12 881.42

4 903.62 868.92 55 916.37 881.67

5 903.87 869.17 56 916.62 881.92

6 904.12 869.42 57 916.87 882.17

7 904.37 869.67 58 917.12 882.42

8 904.62 869.92 59 917.37 882.67

9 904.87 870.17 60 917.62 882.92

10 905.12 870.42 61 917.87 883.17

11 905.37 870.67 62 918.12 883.42

12 905.62 870.92 63 918.37 883.67

13 905.87 871.17 64 918.62 883.92

14 906.12 871.42 65 918.87 884.17

15 906.37 871.67 66 919.12 884.42

16 906.62 871.92 67 919.37 884.67

17 906.87 872.17 68 919.62 884.92

18 907.12 872.42 69 919.87 885.17

19 907.37 872.67 70 920.12 885.42

20 907.62 872.92 71 920.37 885.67

21 907.87 873.17 72 920.62 885.92

22 908.12 873.42 73 920.87 886.17

23 908.37 873.67 74 921.12 886.42

24 908.62 873.92 75 921.37 886.67

25 908.87 874.17 76 921.62 886.92

26 909.12 874.42 77 921.87 887.17

27 909.37 874.67 78 922.12 887.42

28 909.62 874.92 79 922.37 887.67

29 909.87 875.17 80 922.62 887.92

30 910.12 875.42 81 922.87 888.17

31 910.37 875.67 82 923.12 888.42

32 910.62 875.92 83 923.37 888.67

33 910.87 876.17 84 923.62 888.92

34 911.12 876.42 85 923.87 889.17

35 911.37 876.67 86 924.12 889.42

36 911.62 876.92 87 924.37 889.67

37 911.87 877.17 88 924.62 889.92

38 912.12 877.42 89 924.87 890.17

39 912.37 877.67 90 925.12 890.42

40 912.62 877.92 91 925.37 890.67

41 912.87 878.17 92 925.62 890.92

42 913.12 878.42 93 925.87 891.17

43 913.37 878.67 94 926.12 891.42

44 913.62 878.92 95 926.37 891.67

45 913.87 879.17 96 926.62 891.92

46 914.12 879.42 97 926.87 892.17

47 914.37 879.67 98 927.12 892.42

48 914.62 879.92 99 927.37 892.67

49 914.87 880.17 100 927.62 892.92

50* 915.12 880.42

= Also available in Parallel Mode

CHANNEL SELECTION

Parallel Selection

All HP3 receiver models feature eight

parallel selectable channels. Parallel

Mode is selected by grounding the

MODE line. In this mode, channel

selection is determined by the logic

states of pins CS0, CS1, and CS2, as

shown in the adjacent table. A ‘0’

represents ground and a ‘1’ the positive supply. The on-board microprocessor

performs all PLL loading functions, eliminating external programming and

allowing channel selection via DIP switches or a product’s processor.

Serial Selection

In addition to the Parallel Mode, PS versions of the HP3 also feature 100 serially

selectable channels. The Serial Mode is entered when the MODE line is left open

or held high. In this condition, CS1 and CS2 become a synchronous serial port,

with CS1 serving as the clock line and CS2 as the data line. The module is easily

programmed by sending and latching the binary number (0 to 100) of the desired

channel (see the adjacent Serial Channel Selection Table). With no additional

effort, the module’s microprocessor handles the complex PLL loading functions.

The Serial Mode is

straightforward; however,

minimum timings and bit

order must be followed.

Loading is initiated by

taking the clock line high

and the data line low as

shown. The eight-bit

channel number is then

clocked-in one bit at a

time, with the LSB first.

There is no maximum time for this process, only the minimum times that must be

observed. After the eighth bit, both the clock and data lines should be taken high

to trigger the automatic data latch. A typical software routine can complete the

loading sequence in under 200uS. Sample code is available on the Linx website.

NOTE: When the module is powered up in the Serial Mode, it will default to channel 50 until changed

by user software. This allows testing apart from external programming and prevents out-of-band

operation. When programmed properly, the dwell time on this default channel can be less than 200uS.

Channel 50 is not counted as a usable channel since data errors may occur as transmitters also default

to channel 50 on startup. If a loading error occurs, such as a channel number >100 or a timing problem,

the receiver will default to serial channel 0. This is useful for debugging as it verifies serial port activity.

Table 2: Parallel Channel Selection Table

Variable Data

Note 3

Note 2

Note 1

12345678

25µs

5µs

8µs

5µs

Data

Clock

1ms

(T0) Time between packets or prior to data startup ................................1mS min.

(T1) Data-LO / Clock-HI to Data-LO / Clock-LO .......................................25

S min.

(T2) Clock-LO to Clock-HI ...........................................................................5

S min.

(T3) Clock-HI to Clock-LO ...........................................................................8

S min.

(T4) Data-HI / Clock-HI .................................................................................5

S min.

Total Packet Time ......................................................................................157

S min.

1) Loading begins when clock line is high and data line is taken low

2) Ensure that edge is fully risen prior to high-clock transition

3) Both lines high triggers automatic latch

Figure 13: PLL Serial Data Timing

CS2 CS1 CS0 Channel Frequency

0 0 0 0 903.37

0 0 1 1 906.37

0 1 0 2 907.87

0 1 1 3 909.37

1 0 0 4 912.37

1 0 1 5 915.37

1 1 0 6 919.87

1 1 1 7 921.37

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

RXM-900-HP3-PPO

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