TS652ID

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TS652
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DIGITAL INPUTS
SIMPLIFIED SCHEMATIC
The TS652 consists of two independent channels.
Each channel has two stages. The first is a very low noise digitally controlled variable gain amplifier (range
0 to 18dB).
The TS652 features a high input impedance and a low noise current. To minimize the overall noise figure,
the source impedance must be less than 3k.
This value gives an equal contribution of voltage and current noises.
The second stage is a gain/attenuation stage (+12dB to -9dB) featuring a low output impedance.
This output stage can drive loads as low as 500.
POWER DOWN MODE POSITION
Symbol Parameter Min. Typ. Max. Unit
GC1, GC2, GC3
and GC4
Low Level 0 0.8
V
High Level 2 3.3
+
_
_
+
+
_
_
+
v
v
GAIN CONTROL
LOGIC DECODER
Input1
+
_
_
+
v
Input2
+Vcc2
Digital GND
(DGND)
Ouput2
Ouput1
+Vcc1
-Vcc
Analog GND
(AGND)
GC2
GC1
GC3
GC4
v
v
v
Power
Down
+Vcc
-Vcc
+Vcc
-Vcc
Power Down
Input Output
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TS652
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BANDWIDTH
The small signal bandwidth is almost constant for gains between +18dB to 0dB and is in the order of
52MHz to 70MHz respectively. For 30dB gain the bandwidth is around 18MHz.
The power bandwidth is typically equal to 30MHz for 2V peak to peak signals.
MAXIMUM INPUT LEVEL
The input level must not exceed the following values :
negative peak value: must be greater than -V
CC
+ 1.5V
positive peak value: must be less than +V
CC
- 1.5V
For example, if a
±6V power supply is used, the input signal can swing between -4.5V and +4.5V.
These values are due to common mode input range limitations of the input stage of the first amplifier.
Some other limitations may occur, due to the slew rate of the first operational amplifier (typically in the or-
der of 300V/µs). This means that the maximum input signal decreases at high frequency.
SINGLE SUPPLY OPERATION
The incoming signal is AC coupled to the inputs.
The TS652 can be used either with a dual or a single supply. If a single supply is used, the inputs are bi-
ased to the mid supply voltage (+V
CC/2
). This bias network must be carefully designed, in order to reject
any noise present on the supply rail.
The AGND pin (9) must be connected to +V
CC/2
. The bias current of the second stage (inverting structure)
is 8µA for both amplifiers. A resistor divider structure can be used. Two resistances should be chosen by
considering 8µA as the 1% of the total current through these resistances. For a single +12V supply volt-
age, two resistances of 7.5k can be used. The differential input consists of a high pass circuit, formed by
the 1µF capacitor and a 1k resistance and gives a break frequency of 160Hz.
SINGLE +12V SUPPLY OF THE TS652
+Vcc2
Input 1
Input 2
-Vcc
DGND
GC1
GC2
GC3
GC4
Output 1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Output 2
AGND
Power Down
+Vcc1
Gain Control
Logic Decoder
10nF 1µF
7.5k
7.5k
12V
10nF 1µF
47k
47k
12V
1k
1k
IN+
IN-
10nF
100nF 10µF
12V
10nF
100nF
1µF
1µF
TS652
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TS652
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GAIN CONTROL
The gain and the power down mode is programmed with a 4 bit digital word :
The gain is the same for both channels.
The digital inputs are CMOS compatible. The supply voltage of the logic decoder used to transcode the digital word can be either 3.3V or 5V or V
CC
.
Digital
Control
GC4....GC1
MSB LSB
Total Gain
(dB)
First Stage
Gain
(dB)
Second Stage
Gain
(dB)
Maximum
Input Level
Bandwidth
Small Signal
Eq. Input
Noise
(nV/
Hz)
$0000 -9 0 -9 2.8Vrms 110mHZ 29
$0001 -6 0 -6 2.8Vrms 100MHz 26
$0010 -3 0 -3 2.8Vrms 85MHz 23
$0011 0 0 0 2.8Vrms 69MHz 22
$0100 3 3 0 2Vrms 63MHz 16
$0101 6 6 0 1.4Vrms 58MHz 12
$0110 9 9 0 1Vrms 56MHz 9
$0111 12 12 0 0.7Vrms 55MHz 7
$1000 15 15 0 0.5Vrms 54MHz 6
$1001 18 18 0 0.35Vrms 52MHz 4.8
$1010 21 21 3 0.25Vrms 42MHz 4.7
$1011 24 24 6 175mVrms 30MHz 4.7
$1100 27 27 9 125mVrms 24MHz 4.6
$1101 30 30 12 88mVrms 18MHz 4.6
$1110 30 30 12 88mVrms 18MHz 4.6
$1111 30 30 12 88mVrms 18MHz 4.6

TS652ID

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Differential Amplifiers Diff Variable Gain
Lifecycle:
New from this manufacturer.
Delivery:
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