Fremont Micro Devices 93C46/A, 93C56/A, 93C66/A
© 2013 Fremont Micro Devices Inc. Confidential Rev. 0.8 DS93CXX-A-page5
INSTRUCTION SETS DESCRIPTION
(A) READ
The Read (READ) instruction contains the Address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the serial
output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It
should be noted that when a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
(B) ERASE/WRITE ENABLE
To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when
power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any
programming instructions can be carried out. Please note that once in the Erase/Write Enable state,
programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V
CC
power is removed from the part.
(C) ERASE/WRITE DISABLE
To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all
programming modes and should be executed after all programming operations. The operation of the
READ instruction is independent of both the EWEN and EWDS instructions and can be executed at
any time.
(D) ERASE
The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1”
state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The
DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a
minimum of 250 ns (t
CS
). A logic “1” at pin DO indicates that the selected memory location has been
erased, and the part is ready for another instruction.
(E) WRITE
The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory
location. The self-timed programming cycle, t
WP
, starts after the last bit of data is received at serial
data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (t
CS
). A logic “0” at DO indicates that programming is still in
progress. A logic “1” indicates that the memory location at the specified address has been written with
the data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of the self-timed
programming cycle, t
WP
.
(F) ERASE ALL
The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is
primarily used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is
brought high after being kept low for a minimum of 250 ns (t
CS
). The ERAL instruction is valid only at
V
CC
= 5.0V ± 10%.
(G) WRITE ALL
The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the
instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being
kept low for a minimum of 250 ns (t
CS
). The WRAL instruction is valid only at V
CC
= 5.0V ± 10%.
