Data Sheet HMC521ALC4
Rev. 0 | Page 5 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
1
3
4
2
7
NIC
NIC
GND
RF
5
6
GND
NIC
NIC
14
GND
15
LO
16
GND
17
NIC
18
NIC
NIC
8
NIC
9
IF1
10
NIC
11
IF2
12
19
GND
NIC
20
NIC
21
NIC
22
NIC
23
NIC
24
NIC
NOTES
1.
NIC = NOT INTERNALLY CONNECTED.
THESE PINS
ARE NOT CONNECTED INTERNALLY.
2.
EXPOSED
P
AD. THE EXPOSED PAD MUST BE
CONNECTED TO THE GND PIN.
16780-002
HMC521ALC4
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration 7
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 6 to 8, 10,
13, 17 to 24
NIC Not Internally Connected. These pins are not connected internally.
3, 5, 12, 14, 16 GND
Ground. These pins and package bottom must be connected to RF and dc ground. See Figure 3 for the
GND interface schematic.
Radio Frequency Port. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RF interface
schematic.
9 IF1
First Quadrature Intermediate Frequency Port. This pin is dc-coupled. For applications not requiring
operation to dc, dc block this port externally using a series capacitor of a value chosen to pass the
necessary IF frequency range. For operation to dc, these pins must not source or sink more than 2 mA of
current. Otherwise, die malfunction or die failure may result. See Figure 5 for the IFx interface schematic.
11 IF2
Second Quadrature Intermediate Frequency Port. This pin is dc-coupled. For applications not requiring
operation to dc, dc block this port externally using a series capacitor of a value chosen to pass the
necessary IF frequency range. For operation to dc, these pins must not source or sink more than 2 mA of
current. Otherwise, die malfunction or die failure may result. See Figure 5 for the IFx interface schematic.
15 LO
Local Oscillator Port. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the LO interface
schematic.
EPAD Exposed Pad. The exposed pad must be connected to the GND pin.
INTERFACE SCHEMATICS
Figure 3. GND Interface Schematic
Figure 4. LO Interface Schematic
Figure 5. IFx Interface Schematic
Figure 6. RF Interface Schematic