74AC273, 74ACT273 — Octal D-Type Flip-Flop
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC273, 74ACT273 Rev. 1.6.0
January 2008
74AC273, 74ACT273
Octal D-Type Flip-Flop
Features
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Ideal buffer for microprocessor or memory
■
Eight edge-triggered D-type flip-flops
■
Buffered common clock
■
Buffered, asynchronous master reset
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See 377 for clock enable version
■
See 373 for transparent latch version
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See 374 for 3-STATE version
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Outputs source/sink 24mA
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74ACT273 has TTL-compatible inputs
General Description
The AC273 and ACT273 have eight edge-triggered
D-type flip-flops with individual D-type inputs and Q
outputs. The common buffered Clock (CP) and Master
Reset (MR
) input load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR
input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74AC273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
