Data Sheet ADuM1410/ADuM1411/ADuM1412
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
ADuM1410BRWZ/ADuM1411BRWZ/
ADuM1412BRWZ
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
25 35 60 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 5 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
30 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
5 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
All Models
Output Rise/Fall Time (10% to 90%) t
R
/t
F
C
L
= 15 pF, CMOS signal levels
5 V/3 V Operation 2.5 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity at
Logic High Output
7
|CM
H
| 25 35 kV/µs
V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output
7
|CM
L
| 25 35 kV/µs
V
Ix
= 0 V, V
CM
= 1000 V, transient
magnitude = 800 V
Refresh Rate f
r
3 V/5 V Operation 1.1 Mbps
Input Enable Time
8
t
ENABLE
2.0 µs V
IA
, V
IB
, V
IC
, V
ID
= 0 V or V
DD1
Input Disable Time
8
t
DISABLE
5.0 µs V
IA
, V
IB
, V
IC
, V
ID
= 0 V or V
DD1
Input Dynamic Supply Current
per Channel
9
I
DDI (D)
0.12
mA/
Mbps
3 V Operation
0.07
mA/
Mbps
Output Dynamic Supply Current per
Channel
9
I
DDO (D)
5 V Operation
0.04
mA/
Mbps
3 V Operation
0.02
mA/
Mbps
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. |CM
L
| is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when V
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
DISABLE
is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL
2
logic state (see Table 14).
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. M | Page 9 of 22
