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ADUM2251ARIZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ADuM2250/ADuM2251 Data Sheet
Rev. D | Page 10 of 16
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADuM2250/ADuM2251 interface on each side to I
2
C sig-
nals. Internally, the bidirectional I
2
C signals are split into two
unidirectional channels communicating in opposite directions
via dedicated iCoupler isolation channels. One channel of each
pair (the Side 1 input of each input/output pin in Figure 6)
implements a special input buffer and output driver that can
differentiate between externally generated inputs and its own
output signals. It transfers only externally generated input
signals to the corresponding Side 2 data or clock pin.
Both the Side 1 and Side 2 I
2
C pins are designed to interface to
an I
2
C bus operating in the 3.0 V to 5.5 V range. A logic low on
either side causes the corresponding input/output pin across the
coupler to be pulled low enough to comply with the logic low
threshold requirements of other I
2
C devices on the bus. Bus
contention and latch-up are avoided by guaranteeing that the
input low threshold at SDA
1
or SCL
1
is at least 50 mV less than
the output low signal at the same pin. This prevents an output
logic low at Side 1 from being transmitted back to Side 2 and
pulling down the I
2
C bus by latching the state.
Because the Side 2 logic levels/thresholds and drive capabilities
comply fully with standard I
2
C values, multiple ADuM2250/
ADuM2251 devices connected to a bus by their Side 2 pins can
communicate with each other and with other I
2
C-compatible
devices, as shown in Figure 7. Note the distinction between I
2
C
compatibility and I
2
C compliance. I
2
C compatibility refers to situ-
ations in which the logic levels or drive capability of a component
do not necessarily meet the requirements of the I
2
C specification
but still allow the component to communicate with an I
2
C-com-
pliant device. I
2
C compliance refers to situations in which the
logic levels and drive capability of a component fully meet the
requirements of the I
2
C specification.
Because the Side 1 pin has a modified output level/input threshold,
Side 1 of the ADuM2250/ADuM2251 can communicate only with
devices that are fully compliant with the I
2
C standard. In other
words, Side 2 of the ADuM2250/ADuM2251 is I
2
C-compliant,
whereas Side 1 is only I
2
C-compatible.
The Side 1 input/output pins must not be connected to other
I
2
C buffers that implement a similar scheme of dual input/output
threshold detection. This latch-up prevention scheme is
implemented in several popular I
2
C level shifting and bus
extension products currently available from Analog Devices
and other manufacturers. Care should be taken to review the
data sheet of potential I
2
C bus buffering products to ensure that
only one buffer on a bus segment implements a dual threshold
scheme.
A bus segment is a portion of the I
2
C bus that is isolated from
other portions of the bus by galvanic isolation, bus extenders, or
level shifting buffers. Table 11 shows how multiple ADuM2250/
ADuM2251 components can coexist on a bus as long as two
Side 1 buffers are not connected to the same bus segment.
Table 11. ADuM2250/ADuM2251 Buffer Compatibility
Side 1 Side 2
Side 1
No Yes
Side 2
Yes Yes
The output logic low levels are independent of the V
DD1
and
V
DD2
voltages. The input logic low threshold at Side 1 is also
independent of V
DD1
. However, the input logic low threshold at
Side 2 is designed to be at 0.3 V
DD2
, consistent with I
2
C require-
ments. The Side 1 and Side 2 input/output pins have open-
collector outputs whose high levels are set via pull-up resistors
to their respective supply voltages.
DECODE
ENCODE
ENCODE
DECODE
DECODE
ENCODE
ENCODE
DECODE
GND
1
NC
V
DD1
NC
SDA
1
SCL
1
NC
GND
1
GND
2
NC
V
DD2
NC
SDA
2
SCL
2
NC
GND
2
06670-006
8
7
5
6
4
3
2
1
12
11
13
14
15
16
10
ADuM2250
SYMBOL INDICATES A DUAL THRESHOLD INPUT BUFFER.
NC = NO CONNECT
9
Figure 6. ADuM2250 Block Diagram
Figure 7 shows a typical application circuit, including the pull-up
resistors required for both Side 1 and Side 2 buses. Bypass capac-
itors with values from 0.01 μF to 0.1 μF are required between
V
DD1
and GND
1
and between V
DD2
and GND
2
. The 200 Ω resistor
shown in Figure 7 is required for latch-up immunity if the ambient
temperature can be between 105°C and 125°C.
V
DD1
OPTIONAL
200Ω
SDA
1
SCL
1
GND
1
V
DD2
SDA
2
SCL
2
GND
2
8
7
5
6
4
3
2
1
9
12
11
13
14
15
16
10
ADuM2250
06670-007
MICRO-
PROCESSOR
OR
SECONDARY
BUS
SEGMENT
I
2
C BUS
Figure 7. Typical Isolated I
2
C Interface Using the ADuM2250
Data Sheet ADuM2250/ADuM2251
STARTUP
Both the V
DD1
and V
DD2
supplies have an undervoltage lockout
feature that prevents the signal channels from operating unless
certain criteria are met. This feature prevents the possibility of
input logic low signals pulling down the I
2
C bus inadvertently
during power-up/power-down.
For the signal channels to be enabled, the following criteria
must be met:
• Both supplies must be at least 2.5 V.
• At least 40 μs must elapse after both supplies exceed the
internal start-up threshold of 2.0 V.
Until both criteria are met for both supplies, the ADuM2250/
ADuM2251 outputs are pulled high, thereby ensuring a startup
that avoids any disturbances on the bus. Figure 8 and Figure 9
illustrate the supply conditions for fast and slow input supply
slew rates.
SUPPLY VALID
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
MINIMUM VALID SUPPLY, 2.5V
INTERNAL START-UP
THRESHOLD, 2.0V
40µs
06670-008
Figure 8. Start-Up Condition, Supply Slew Rate > 12.5 V/ms
SUPPLY VALID
MINIMUM RECOMMENDED
OPERA
TING SUPPLY, 3.0V
MINIMUM VALID SUPPLY, 2.5V
INTERNAL START-UP
THRESHOLD, 2.0V
40µs
06670-009
Figure 9. Start-Up Condition, Supply Slew Rate < 12.5 V/ms
CAPACITIVE LOAD AT LOW SPEEDS
The ADuM2250/ADuM2251 are designed for operation at
speeds up to 1 Mbps. Due to the limited current available on
Side 1 operation at 1 Mbps limits the capacitance that can be
driven at the minimum pull-up value to 40 pF.
Most applications operate at 100 kbps in standard mode or
400 kbps in fast mode. At these lower operating speeds, the
limitation on the load capacitance can be significantly relaxed.
Table 12 shows the maximum capacitance at minimum pull-up
values for standard and fast operating modes. If larger values for
the pull-up resistor are used, the maximum supported capacitance
must be scaled down proportionately so that the rise time does
not increase beyond the values required by the standard.
Table 12. Side 1 Maximum Load Conditions
Maximum Capacitive Load for Side 1
Mode V
DD1
Data Rate (kbps) t
r
(ns) t
f
(ns) R
1
(Ω) C
L1
(pF)
Standard 5 100 1000 187 1600 484
Fast 5 400 300 172 1600 120
Standard 3.3 100 1000 270 1000 771
Fast
3.3
400
300
235
1000
188
Rev. D | Page 11 of 16
ADuM2250/ADuM2251 Data Sheet
MAGNETIC FIELD IMMUNITY
The ADuM2250/ADuM2251 are extremely immune to external
magnetic fields. The limitation on the magnetic field immunity
of the ADuM2250/ADuM2251 is set by the condition in which
induced voltage in the receiving coil of the transformer is suffi-
ciently large to either falsely set or reset the decoder. The following
analysis defines the conditions under which this may occur. The
3 V operating condition of the ADuM2250/ADuM2251 is
examined because it represents the most susceptible mode of
operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑ πr
n
2
; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
r
n
is the radius of the n
th
turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM2250/
ADuM2251 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field is calculated, as shown in
Figure 10.
MAGNETIC FIELD FREQUENCY (Hz)
100
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06670-010
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
Figure 10. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maxi-
mum allowable magnetic field of 0.2 kgauss induces a voltage of
0.25 V at the receiving coil. This voltage is approximately 50% of
the sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse (and
is of the worst-case polarity), it reduces the received pulse from
>1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of
the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM2250/ADuM2251 transformers. Figure 11 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown in Figure 11, the ADuM2250/
ADuM2251 are extremely immune and can be affected only by
extremely large currents operated at high frequency very close
to the component. For the 1 MHz example, a 0.5 kA current
must be placed 5 mm away from the ADuM2250/ADuM2251
to affect the operation of the component.
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces can
induce error voltages sufficiently large to trigger the thresholds
of succeeding circuitry. Exercise care in the layout of such traces
to avoid this possibility.
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE CURRENT (kA)
1000
100
10
1
0.1
0.01
1k 10k
100M100k 1M
10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
06670-011
Figure 11. Maximum Allowable Current for Various
Current-to-ADuM2250/ADuM2251 Spacings
Rev. D | Page 12 of 16
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADUM2251ARIZ-RL

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Digital Isolators Hot-Swappable Dual I2C 5kV
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