RX6000 Datasheet RX6000 | P7-P9

RX6000 (R) 10/20/14 Page 7 of 10

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Sleep and Wake-Up Timing

The maximum transition time from the receive mode to the power-

down (sleep) mode t

is 10 µs after CNTRL1 and CNTRL0 are

both low (1 µs fall time).

The maximum transition time t

from the sleep mode to the

receive mode is 3*t

BBC

, where t

BBC

is the BBOUT-CMPIN

coupling-capacitor time constant. When the operating temperature

is limited to 60 oC, the time required to switch from sleep to receive

is dramatically less for short sleep times, as less charge leaks

away from the BBOUT- CMPIN coupling capacitor.

AGC Timing

The maximum AGC engage time t

AGC

is 5 µs after the reception of

a -30 dBm RF signal with a 1 µs envelope rise time.

The minimum AGC hold-in time is set by the value of the capacitor

at the AGCCAP pin. The hold-in time t

AGH

= C

AGC

/19.1, where

AGH

is in µs and C

AGC

is in pF.

Peak Detector Timing

The Peak Detector attack time constant is set by the value of the

capacitor at the PKDET pin. The attack time t

PKA

= C

PKD

/4167,

where t

PKA

is in µs and C

PKD

is in pF. The Peak Detector decay

time constant t

PKD

= 1000*t

PKA

Pulse Generator Timing

In the low data rate mode, the interval t

PRI

between the falling edge

of an ON pulse to the first RF amplifier and the rising edge of the

next ON pulse to the first RF amplifier is set by a resistor R

between the PRATE pin and ground. The interval can be adjusted

between 0.1 and 5 µs with a resistor in the range of 51 K to 2000

K. The value of the R

is given by:

= 404* t

PRI

+ 10.5, where t

PRI

is in µs, and R

is in kilohms

In the high data rate mode (selected at the PWIDTH pin) the

receiver RF amplifiers operate at a nominal 50%-50% duty cycle.

In this case, the period t

PRC

from the start of an ON pulse to the

first RF amplifier to the start of the next ON pulse to the first RF

amplifier is controlled by the PRATE resistor over a range of 0.1 to

1.1 µs using a resistor of 11 K to 220 K. In this case R

is given

by:

= 198* t

PRC

- 8.51, where t

PRC

is in µs and R

is in kilohms

In the low data rate mode, the PWIDTH pin sets the width of the

ON pulse to the first RF amplifier t

PW1

with a resistor R

ground (the ON pulse width to the second RF amplifier t

PW2

is set

at 1.1 times the pulse width to the first RF amplifier in the low data

rate mode). The ON pulse width t

PW1

can be adjusted between

0.55 and 1 µs with a resistor value in the range of 200 K to 390 K.

The value of R

is given by:

= 404* t

PW1

- 18.6, where t

PW1

is in µs and R

is in kilohms

However, when the PWIDTH pin is connected to Vcc through a 1

M resistor, the RF amplifiers operate at a nominal 50%-50% duty

cycle, facilitating high data rate operation. In this case, the RF

amplifiers are controlled by the PRATE resistor as described

above.

LPF Group Delay

The low-pass filter group delay is a function of the filter 3 dB

bandwidth, which is set by a resistor R

LPF

to ground at the LPFADJ

pin. The minimum 3 dB bandwidth f

LPF

= 1445/R

LPF

, where f

LPF

in kHz, and R

LPF

is in kilohms.

The maximum group delay t

FGD

= 1750/f

LPF

= 1.21*R

LPF

, where

FGD

is in µs, f

LPF

in kHz, and R

LPF

in kilohms.

Receiver Event Timing, 3.0 Vdc, -40 to +85 °C

Event Symbol Time

Min/

Max

Test Conditions Notes

Turn On to Receive t

3*t

BBC

+ 15 ms max 10 ms supply voltage rise time time until receiver operational

Sleep to RX t

3*t

BBC

max 1 µs CNTRL0/CNTROL 1 rise

times

time until receiver operational

RX to Sleep t

10 µs max 1 µs CNTRL0/CNTROL 1 fall

times

time until receiver is in power-down mode

AGC Engage t

AGC

5 µs max 1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain

AGE Hold-In t

AGH

AGC

/19.1 min CAGC in pF, t

AGH

in µs user selected; longer than t

PKD

PKDET Attack Time Constant t

PKA

PKD

/4167 min C

PKD

in pF, t

PKA

in µs user selected

PKDET Decay Time Constant t

PKD

1000*t

PKA

min t

PKD

and t

PKA

in µs slaved to attack time

PRATE Interval t

PRI

0.1 to 5 µs range low data rate mode user selected mode

PWIDTH RFA1 t

PW1

0.55 to 1 µs range low data rate mode user selected mode

PWIDTH RFA2 t

PW2

1.1*t

PW1

range low data rate mode user selected mode

PRATE Cycle t

PRC

0.1 to 1.1 µs range high data rate mode user selected mode

PWIDTH High (RFA1 & RFA2) t

PWH

0.05 to 0.55 µs range high data rate mode user selected mode

LPF Group Delay t

FGD

1750/f

LPF

max t

FGD

in µs, f

LPF

in kHz user selected

LPF 3 dB Bandwidth f

LPF

1445/R

LPF

min f

LPF

in kHz, R

LPF

in kilohms user selected

BBOUT-CMPIN Time Constant t

BBC

0.064*C

BBO

min t

BBC

in µs, C

BBO

in pF user selected

Table 1

RX6000 (R) 10/20/14 Page 8 of 10

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Pin Descriptions

Pin Name Description

1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.

2 VCC1 VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor,

which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.

3 AGCCAP This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the AGC will hold-

in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time t

AGH

, the capacitor value C

AGC

is:

AGC

= 19.1* t

AGH

, where t

AGH

is in µs and C

AGC

is in pF

A ±10% ceramic capacitor should be used at this pin. The value of C

AGC

given above provides a hold-in time between t

AGH

and 2.65* t

AGH

, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride

through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the

peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will

be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when

using OOK modulation with data pulses of at least 30 µs. AGC operation can be defeated by connecting this pin to Vcc.

Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The AGC can be

latched on once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation

depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down

(sleep) mode.

4 PKDET This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and

decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the

base-band time constant. For a given base-band capacitor C

BBO

, the capacitor value C

PKD

is:

PKD

= 0.33* C

BBO

, where C

BBO

and C

PKD

are in pF

A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t

PKA

and 1.5* t

PKA

with variations

in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a 200 K

load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The AGC hold-in time

can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates

and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin and

the THLD2 pin can be left unconnected, and the AGC pin can be connected to Vcc to reduce the number of external compo-

nents needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode.

5 BBOUT BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C

BBO

for internal

data slicer operation. The time constant t

BBC

for this connection is:

BBC

= 0.064*C

BBO

, where t

BBC

is in µs and C

BBO

is in pF

A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t

BBC

and

1.8*t

BBC

with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend

on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common criteria

is to set the time constant for no more than a 20% voltage droop during SP

MAX

. For this case:

BBO

= 70*SP

MAX

, where SP

MAX

is the maximum signal pulse width in µs and C

BBO

is in pF

The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped-

ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes

about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak

signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply volt-

age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in

parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must

be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function

is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin

becomes very high, preserving the charge on the coupling capacitor.

6 CMPIN This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of

this pin is 70 K to 100 K.

7 RXDATA RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this

pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high

impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is

high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc +

200 mV.

8 NC This pin may be left unconnected or may be grounded.

RX6000 (R) 10/20/14 Page 9 of 10

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9 LPFADJ This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R

LPF

between this pin and

ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f

LPF

from 4.5 kHz to 1.8 MHz.

The resistor value is determined by:

LPF

= 1445/ f

LPF

, where R

LPF

is in kilohms, and f

LPF

is in kHz

A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f

LPF

and 1.3* f

LPF

with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response.

The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.

Pin Name Description

10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

11 RREF RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%

resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less

than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less

that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.

12 THLD2 THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor R

TH2

between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value

(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV for

a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:

TH2

= 1.67*V, where R

TH2

is in kilohms and the threshold V is in mV

A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-peak

data slicer operation.

13 THLD1 The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R

TH1

to RREF. The threshold is

increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the

resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is 0

to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:

TH1

= 1.11*V, where R

TH1

is in kilohms and the threshold V is in mV

For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1 range

of 0 to 90 mV. The resistor value is given by:

TH1

= 2.22*V, where R

TH1

is in kilohms and the threshold V is in mV

A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for proper

AGC operation.

14 PRATE The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the

first RF amplifier t

PRI

is set by a resistor R

between this pin and ground. The interval t

PRI

can be adjusted between 0.1 and

5 µs with a resistor in the range of 51 K to 2000 K. The value of R

is given by:

= 404* t

PRI

+ 10.5, where t

PRI

is in µs, and R

is in kilohms

A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers

operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t

PRC

from start-to-start

of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K

to 220 K. In this case the value of R

is given by:

= 198* t

PRC

- 8.51, where t

PRC

is in µs and R

is in kilohms

A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional

amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5

pF to maintain stability.

15 PWIDTH The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t

PW1

with a resistor R

to ground (the ON pulse

width to the second RF amplifier t

PW2

is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t

PW1

can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R

is given by:

= 404* t

PW1

- 18.6, where t

PW1

is in µs and R

is in kilohms

A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at

a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by

the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to

less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor

between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.

16 VCC2 VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which

may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.

17 CNTRL1 CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode.

CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS

compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is inter-

preted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a

maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic

level; it cannot be left unconnected.

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