25A512
DS22237C-page 16 Preliminary 2010-2011 Microchip Technology Inc.
2.9 SECTOR ERASE
The SECTOR ERASE instruction will erase all bits
(FFh) inside the given sector. A Write Enable (WREN)
instruction must be given prior to attempting a SECTOR
ERASE. This is done by setting CS
low and then clock-
ing out the proper instruction into the 25A512. After all
eight bits of the instruction are transmitted, the CS
must be brought high to set the write enable latch.
The SECTOR ERASE instruction is entered by driving
CS
low, followed by the instruction code (Figure 2-9)
and two address bytes. Any address inside the sector
to be erased is a valid address.
CS
must then be driven high after the last bit of the
address or the SECTOR ERASE will not execute. Once
the CS is driven high the self-timed SECTOR ERASE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the SECTOR ERASE
cycle is complete.
If a SECTOR ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
See Table 2-3 for Sector Addressing.
FIGURE 2-9: SECTOR ERASE SEQUENCE
SO
SI
SCK
CS
0 234567891011 2122231
0000010115 14 13 12 210
Instruction 16-bit Address
High-Impedance
2010-2011 Microchip Technology Inc. Preliminary DS22237C-page 17
25A512
2.10 CHIP ERASE
The CHIP ERASE instruction will erase all bits (FFh) in
the array. A Write Enable (WREN) instruction must be
given prior to executing a CHIP ERASE. This is done
by setting CS
low and then clocking out the proper
instruction into the 25A512. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch.
The CHIP ERASE instruction is entered by driving the
CS
low, followed by the instruction code (Figure 2-10)
onto the SI line.
The CS
pin must be driven high after the eighth bit of
the instruction code has been given or the CHIP
ERASE instruction will not be executed. Once the CS
pin is driven high the self-timed CHIP ERASE instruc-
tion begins. While the device is executing the CHIP
ERASE instruction the WIP bit in the STATUS register
can be read to determine when the CHIP ERASE
instruction is complete.
The CHIP ERASE instruction is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning ¼,
½, or all of the array is protected.
FIGURE 2-10: CHIP ERASE SEQUENCE
SCK
0 2345671
SI
High-Impedance
SO
CS
111000 11
25A512
DS22237C-page 18 Preliminary 2010-2011 Microchip Technology Inc.
2.11 DEEP POWER-DOWN MODE
Deep Power-Down mode of the 25A512 is its lowest
power consumption state. The device will not respond
to any of the Read or Write commands while in Deep
Power-Down mode, and therefore it can be used as an
additional software write protection feature.
The Deep Power-Down mode is entered by driving C
S
low, followed by the instruction code (Figure 2-11) onto
the SI line, followed by driving CS
high.
If the CS
pin is not driven high after the eighth bit of the
instruction code has been given, the device will not
execute Deep power-down. Once the CS line is driven
high there is a delay (T
DP
) before the current settles to
its lowest consumption.
All instructions given during Deep Power-Down mode
are ignored except the Read Electronic Signature
command (RDID). The RDID command will release
the device from Deep power-down and outputs the
electronic signature on the SO pin, and then returns
the device to Standby mode after delay (T
REL
)
Deep Power-Down mode automatically releases at
device power-down. Once power is restored to the
device it will power-up in the Standby mode.
FIGURE 2-11: DEEP POWER-DOWN SEQUENCE
SCK
0 2345671
SI
High-Impedance
SO
CS
100111 10

25A512T-I/ST

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 512k 64K X 8 1.8V SER EE IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union