MC74VHCT259ADTR2

Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1 Publication Order Number:
MC74VHCT259A/D
MC74VHCT259A
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHCT259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the signal on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non–addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one–of–eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the VHCT259 as an addressable
latch, changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be done while in
the memory mode.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V because it
has full 5 V CMOS level output swings.
The VHCT259A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage—input/output voltage mismatch, battery backup, hot
insertion, etc.
High Speed: t
PD
= 7.6 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 2 µA (Max) at T
A
= 25°C
TTL–Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs and Outputs
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V
http://onsemi.com
Device Package Shipping
ORDERING INFORMATION
MC74VHCT259AD SOIC–16 48 Units/Rail
MC74VHCT259ADR2 SOIC–16 2500 Units/Reel
SOIC–16
D SUFFIX
CASE 751B
TSSOP–16
DT SUFFIX
CASE 948F
SOIC EIAJ–16
M SUFFIX
CASE 966
MARKING DIAGRAMS
1
8
9
16
1
8
16 9
1
16 9
8
VHCT259A
AWLYYWW
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
VHCT
259A
AWLYWW
VHCT259A
ALYW
MC74VHCT259ADT TSSOP–16 96 Units/Rail
MC74VHCT259ADTEL TSSOP–16 2000 Units/Reel
MC74VHCT259AM
SOIC
EIAJ–16
50 Units/Rail
MC74VHCT259AMEL
SOIC
EIAJ–16
2000 Units/Reel
MC74VHCT259ADTR2 TSSOP–16 2500 Units/Reel
MC74VHCT259A
http://onsemi.com
2
Q7
4
3
2
1
A0
A1
A2
NONINVERTING
OUTPUTS
ADDRESS
INPUTS
Figure 1. Logic Diagram
DATA IN
13
15
14
RESET
ENABLE
5
6
7
9
10
11
12
Q6
Q5
Q4
Q3
Q2
Q1
Q0
PIN 16 = V
CC
PIN 8 = GND
MODE SELECTION TABLE LATCH SELECTION TABLE
4
Figure 2. Pin Assignment
5
6
7
8
10
11
12
15
14
13
3
2
1
A0
A1
A2
2
1
4
BIN/OCT
1
0
2
4
3
5
6
7
EN
A0
A1
A2
0
2
DMUX
1
0
2
4
3
5
6
7
G
0
7
ID
R
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
15
14
13
3
2
1
EN
ID
R
4
5
6
7
8
10
11
12
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Enable Reset Mode
L
H
L
HL
H
L
H Addressable Latch
Memory
8–Line Demultiplexer
Reset
Address Inputs
Latch
Addressed
L
H
L
H
H
L
H
CB
A
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
13
14
15
16
9
1
0
11
125
4
3
2
1
8
7
6
A0
A2
A1
GND
DATA IN
ENABLE
RESET
V
CC
Q0
Q1
Q3
Q2
Q7
Q6
Q5
Q4
Figure 3. IEC Logic Symbol
MC74VHCT259A
http://onsemi.com
3
D
Figure 4. Expanded Logic Diagram
DATA INPUT
13 4
Q0
D
5
Q1
D
6
Q2
D
7
Q3
D
9
Q4
D
10
Q5
D
11
Q6
D
12
Q7
3 TO 8
DECODER
ENABLE
14
RESET
15
A0
A1
A2
ADDRESS
INPUTS

MC74VHCT259ADTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Latches 5V CMOS Addressable
Lifecycle:
New from this manufacturer.
Delivery:
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