1-297
ACT
™
1 Series FPGAs
ACT 1 Timing Characteristics
(Worst-Case Commercial Conditions, V
CC
= 4.75 V, T
J
= 70°C)
1
Logic Module Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
PD1
Single Module 2.9 3.4 3.8 4.5 6.5 ns
t
PD2
Dual Module Macros 6.8 7.8 8.8 10.4 15.1 ns
t
CO
Sequential Clk to Q 2.9 3.4 3.8 4.5 6.5 ns
t
GO
Latch G to Q 2.9 3.4 3.8 4.5 6.5 ns
t
RS
Flip-Flop (Latch) Reset to Q 2.9 3.4 3.8 4.5 6.5 ns
Predicted Routing Delays
2
t
RD1
FO=1 Routing Delay 0.9 1.1 1.2 1.4 2.0 ns
t
RD2
FO=2 Routing Delay 1.4 1.7 1.9 2.2 3.2 ns
t
RD3
FO=3 Routing Delay 2.1 2.5 2.8 3.3 4.8 ns
t
RD4
FO=4 Routing Delay 3.1 3.6 4.1 4.8 7.0 ns
t
RD8
FO=8 Routing Delay 6.6 7.7 8.7 10.2 14.8 ns
Sequential Timing Characteristics
3
t
SUD
Flip-Flop (Latch) Data Input Setup 5.5 6.4 7.2 8.5 10.0 ns
t
HD
4
Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns
t
SUENA
Flip-Flop (Latch) Enable Setup 5.5 6.4 7.2 8.5 10.0 ns
t
HENA
Flip-Flop (Latch) Enable Hold 0.0 0.0 0.0 0.0 0.0 ns
t
WCLKA
Flip-Flop (Latch) Clock Active Pulse
Width 6.8 8.0 9.0 10.5 9.8 ns
t
WASYN
Flip-Flop (Latch)
Asynchronous Pulse Width 6.8 8.0 9.0 10.5 9.8 ns
t
A
Flip-Flop Clock Input Period 14.2 16.7 18.9 22.3 20.0 ns
f
MAX
Flip-Flop (Latch) Clock
Frequency (FO = 128) 70 60 53 45 50 MHz
Notes:
1. V
CC
= 3.0 V for 3.3V specifications.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.
4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro.
